Searched refs:SAR_RST_PCIE1_CLOCK_CONFIG_CP0_MASK (Results 1 – 1 of 1) sorted by relevance
62 #define SAR_RST_PCIE1_CLOCK_CONFIG_CP0_MASK (0x1UL << \ macro1323 clk_dir = (reg & SAR_RST_PCIE1_CLOCK_CONFIG_CP0_MASK) >> in mvebu_cp110_comphy_pcie_power_on()