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Searched refs:RSTMGR_CPUxRESETBASELOW_CPU2 (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/common/include/
H A Dsocfpga_reset_manager.h222 #define RSTMGR_CPUxRESETBASELOW_CPU2 0x10D110A8 macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/
H A Dbl31_plat_setup.c272 mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU2, in bl31_plat_set_secondary_cpu_entrypoint()