1 /* 2 * Copyright (c) 2015-2026, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef RPC_REGISTERS_H 8 #define RPC_REGISTERS_H 9 10 #if defined(RCAR_LSI) 11 #define RPC_BASE 0xEE200000U 12 #elif defined(RZA3) 13 #define RPC_BASE 0x10060000U 14 #else 15 #error "SPI Multi I/O Bus Controller base address is not defined" 16 #endif 17 18 #define RPC_CMNCR (RPC_BASE + 0x0000U) 19 #define RPC_SSLDR (RPC_BASE + 0x0004U) 20 #define RPC_DRCR (RPC_BASE + 0x000CU) 21 #define RPC_DRCMR (RPC_BASE + 0x0010U) 22 #define RPC_DROPR (RPC_BASE + 0x0018U) 23 #define RPC_DRENR (RPC_BASE + 0x001CU) 24 #define RPC_SMCR (RPC_BASE + 0x0020U) 25 #define RPC_SMCMR (RPC_BASE + 0x0024U) 26 #define RPC_SMENR (RPC_BASE + 0x0030U) 27 #define RPC_CMNSR (RPC_BASE + 0x0048U) 28 #define RPC_DRDMCR (RPC_BASE + 0x0058U) 29 #define RPC_DRDRENR (RPC_BASE + 0x005CU) 30 #define RPC_PHYCNT (RPC_BASE + 0x007CU) 31 #define RPC_PHYOFFSET1 (RPC_BASE + 0x0080U) 32 #define RPC_PHYOFFSET2 (RPC_BASE + 0x0084U) 33 #define RPC_PHYINT (RPC_BASE + 0x0088U) 34 35 /* CMNCR field */ 36 #define RPC_CMNCR_MD_POS 31 37 #define RPC_CMNCR_MD (1u << RPC_CMNCR_MD_POS) 38 #define RPC_CMNCR_MOIIO3_POS 22 39 #define RPC_CMNCR_MOIIO3 (3u << RPC_CMNCR_MOIIO3_POS) 40 #define RPC_CMNCR_MOIIO2_POS 20 41 #define RPC_CMNCR_MOIIO2 (3u << RPC_CMNCR_MOIIO2_POS) 42 #define RPC_CMNCR_MOIIO1_POS 18 43 #define RPC_CMNCR_MOIIO1 (3u << RPC_CMNCR_MOIIO1_POS) 44 #define RPC_CMNCR_MOIIO0_POS 16 45 #define RPC_CMNCR_MOIIO0 (3u << RPC_CMNCR_MOIIO0_POS) 46 #define RPC_CMNCR_IO3FV_POS 14 47 #define RPC_CMNCR_IO3FV (3u << RPC_CMNCR_IO3FV_POS) 48 #define RPC_CMNCR_IO2FV_POS 12 49 #define RPC_CMNCR_IO2FV (3u << RPC_CMNCR_IO2FV_POS) 50 #define RPC_CMNCR_IO0FV_POS 8 51 #define RPC_CMNCR_IO0FV (3u << RPC_CMNCR_IO0FV_POS) 52 #define RPC_CMNCR_IO_LOW 0u 53 #define RPC_CMNCR_IO_HIGH 1u 54 #define RPC_CMNCR_IO_KEEP 2u 55 #define RPC_CMNCR_IO_HIZ 3u 56 #define RPC_CMNCR_BSZ_POS 0 57 #define RPC_CMNCR_BSZ (3u << RPC_CMNCR_BSZ_POS) 58 #define RPC_CMNCR_BSZ_SINGLE 0u 59 #define RPC_CMNCR_BSZ_DUAL 1u 60 #define RPC_CMNCR_BSZ_OCTA 1u 61 #define RPC_CMNCR_BSZ_HYPER 1u 62 63 /* SSLDR field */ 64 #define RPC_SSLDR_SPNDL_POS 16 65 #define RPC_SSLDR_SPNDL (7u << RPC_SSLDR_SPNDL_POS) 66 #define RPC_SSLDR_SLNDL_POS 8 67 #define RPC_SSLDR_SLNDL (7u << RPC_SSLDR_SLNDL_POS) 68 #define RPC_SSLDR_SCKDL_POS 0 69 #define RPC_SSLDR_SCKDL (7u << RPC_SSLDR_SCKDL_POS) 70 71 /* DRCR field */ 72 #define RPC_DRCR_SSLN_POS 24 73 #define RPC_DRCR_SSLN (1u << RPC_DRCR_SSLN_POS) 74 #define RPC_DRCR_RBURST_POS 16 75 #define RPC_DRCR_RBURST (31u << RPC_DRCR_RBURST_POS) 76 #define RPC_DRCR_RCF_POS 9 77 #define RPC_DRCR_RCF (1u << RPC_DRCR_RCF_POS) 78 #define RPC_DRCR_RBE_POS 8 79 #define RPC_DRCR_RBE (1u << RPC_DRCR_RBE_POS) 80 #define RPC_DRCR_SSLE_POS 0 81 #define RPC_DRCR_SSLE (1u << RPC_DRCR_SSLE_POS) 82 83 /* DREAR field */ 84 #define RPC_DREAR_EAV_POS 16 85 #define RPC_DREAR_EAV (255u << RPC_DREAR_EAV_POS) 86 #define RPC_DREAR_EAC_POS 0 87 #define RPC_DREAR_EAC (7u << RPC_DREAR_EAC_POS) 88 89 /* DRCMR field */ 90 #define RPC_DRCMR_CMD_POS 16 91 #define RPC_DRCMR_CMD (255u << RPC_DRCMR_CMD_POS) 92 #define RPC_DRCMR_OCMD_POS 0 93 #define RPC_DRCMR_OCMD (255u << RPC_DRCMR_OCMD_POS) 94 95 /* DROPR field */ 96 #define RPC_DROPR_OPD3_POS 24 97 #define RPC_DROPR_OPD3 (255u << RPC_DROPR_OPD3_POS) 98 #define RPC_DROPR_OPD2_POS 16 99 #define RPC_DROPR_OPD2 (255u << RPC_DROPR_OPD2_POS) 100 #define RPC_DROPR_OPD1_POS 8 101 #define RPC_DROPR_OPD1 (255u << RPC_DROPR_OPD1_POS) 102 #define RPC_DROPR_OPD0_POS 0 103 #define RPC_DROPR_OPD0 (255u << RPC_DROPR_OPD0_POS) 104 105 /* DRENR field */ 106 #define RPC_DRENR_CDB_POS 30 107 #define RPC_DRENR_CDB (3u << RPC_DRENR_CDB_POS) 108 #define RPC_DRENR_OCDB_POS 28 109 #define RPC_DRENR_OCDB (3u << RPC_DRENR_OCDB_POS) 110 #define RPC_DRENR_ADB_POS 24 111 #define RPC_DRENR_ADB (3u << RPC_DRENR_ADB_POS) 112 #define RPC_DRENR_OPDB_POS 20 113 #define RPC_DRENR_OPDB (3u << RPC_DRENR_OPDB_POS) 114 #define RPC_DRENR_DRDB_POS 16 115 #define RPC_DRENR_DRDB (3u << RPC_DRENR_DRDB_POS) 116 #define RPC_DRENR_DB_4BIT 2u 117 #define RPC_DRENR_DB_1BIT 0u 118 #define RPC_DRENR_DME_POS 15 119 #define RPC_DRENR_DME (1u << RPC_DRENR_DME_POS) 120 #define RPC_DRENR_CDE_POS 14 121 #define RPC_DRENR_CDE (1u << RPC_DRENR_CDE_POS) 122 #define RPC_DRENR_OCDE_POS 12 123 #define RPC_DRENR_OCDE (1u << RPC_DRENR_OCDE_POS) 124 #define RPC_DRENR_ADE_POS 8 125 #define RPC_DRENR_ADE (15u << RPC_DRENR_ADE_POS) 126 #define RPC_DRENR_ADE_3BYTE 7u 127 #define RPC_DRENR_ADE_4BYTE 15u 128 #define RPC_DRENR_ADE_OPI 12u 129 #define RPC_DRENR_ADE_HYPER 4u 130 #define RPC_DRENR_ADE_NONE 0u 131 #define RPC_DRENR_OPDE_POS 4 132 #define RPC_DRENR_OPDE (15u << RPC_DRENR_OPDE_POS) 133 #define RPC_DRENR_OPDE_NONE 0u 134 #define RPC_DRENR_OPDE_1BYTE 8u 135 #define RPC_DRENR_OPDE_2BYTE 12u 136 #define RPC_DRENR_OPDE_3BYTE 14u 137 #define RPC_DRENR_OPDE_4BYTE 15u 138 139 /* DRENR field */ 140 #define RPC_DRENR_CDB_POS 30 141 #define RPC_DRENR_CDB (3u << RPC_DRENR_CDB_POS) 142 #define RPC_DRENR_OCDB_POS 28 143 #define RPC_DRENR_OCDB (3u << RPC_DRENR_OCDB_POS) 144 #define RPC_DRENR_ADB_POS 24 145 #define RPC_DRENR_ADB (3u << RPC_DRENR_ADB_POS) 146 #define RPC_DRENR_OPDB_POS 20 147 #define RPC_DRENR_OPDB (3u << RPC_DRENR_OPDB_POS) 148 #define RPC_DRENR_DRDB_POS 16 149 #define RPC_DRENR_DRDB (3u << RPC_DRENR_DRDB_POS) 150 #define RPC_DRENR_DB_4BIT 2u 151 #define RPC_DRENR_DB_1BIT 0u 152 #define RPC_DRENR_DME_POS 15 153 #define RPC_DRENR_DME (1u << RPC_DRENR_DME_POS) 154 #define RPC_DRENR_CDE_POS 14 155 #define RPC_DRENR_CDE (1u << RPC_DRENR_CDE_POS) 156 #define RPC_DRENR_OCDE_POS 12 157 #define RPC_DRENR_OCDE (1u << RPC_DRENR_OCDE_POS) 158 #define RPC_DRENR_ADE_POS 8 159 #define RPC_DRENR_ADE (15u << RPC_DRENR_ADE_POS) 160 #define RPC_DRENR_ADE_3BYTE 7u 161 #define RPC_DRENR_ADE_4BYTE 15u 162 #define RPC_DRENR_ADE_OPI 12u 163 #define RPC_DRENR_ADE_HYPER 4u 164 #define RPC_DRENR_ADE_NONE 0u 165 #define RPC_DRENR_OPDE_POS 4 166 #define RPC_DRENR_OPDE (15u << RPC_DRENR_OPDE_POS) 167 #define RPC_DRENR_OPDE_NONE 0u 168 #define RPC_DRENR_OPDE_1BYTE 8u 169 #define RPC_DRENR_OPDE_2BYTE 12u 170 #define RPC_DRENR_OPDE_3BYTE 14u 171 #define RPC_DRENR_OPDE_4BYTE 15u 172 173 /* DRDMCR field */ 174 #define RPC_DRDMCR_DMCYC_POS 0 175 #define RPC_DRDMCR_DMCYC (31u << RPC_DRDMCR_DMCYC_POS) 176 177 /* DRDRENR field */ 178 #define RPC_DRDRENR_HYPE_POS 12 179 #define RPC_DRDRENR_HYPE (7u << RPC_DRDRENR_HYPE_POS) 180 #define RPC_DRDRENR_SPI 0u 181 #define RPC_DRDRENR_DDR 5u 182 #define RPC_DRDRENR_OCTADDR 4u 183 #define RPC_DRDRENR_ADDRE_POS 8 184 #define RPC_DRDRENR_ADDRE (1u << RPC_DRDRENR_ADDRE_POS) 185 #define RPC_DRDRENR_OPDRE_POS 4 186 #define RPC_DRDRENR_OPDRE (1u << RPC_DRDRENR_OPDRE_POS) 187 #define RPC_DRDRENR_DRDRE_POS 0 188 #define RPC_DRDRENR_DRDRE (1u << RPC_DRDRENR_DRDRE_POS) 189 190 /* PHYCNT field */ 191 #define RPC_PHYCNT_CAL_POS 31 192 #define RPC_PHYCNT_CAL (1u << RPC_PHYCNT_CAL_POS) 193 #define RPC_PHYCNT_ALT_ALIGN_POS 30 194 #define RPC_PHYCNT_ALT_ALIGN (1u << RPC_PHYCNT_ALT_ALIGN_POS) 195 #define RPC_PHYCNT_OCTA_POS 22 196 #define RPC_PHYCNT_OCTA (3u << RPC_PHYCNT_OCTA_POS) 197 #define RPC_PHYCNT_OCTA_DDR_ALT 1u 198 #define RPC_PHYCNT_OCTA_DDR_SEQ 2u 199 #define RPC_PHYCNT_EXDS_POS 21 200 #define RPC_PHYCNT_EXDS (1u << RPC_PHYCNT_EXDS_POS) 201 #define RPC_PHYCNT_OCT_POS 20 202 #define RPC_PHYCNT_OCT (1u << RPC_PHYCNT_OCT_POS) 203 #define RPC_PHYCNT_HS_POS 18 204 #define RPC_PHYCNT_HS (1u << RPC_PHYCNT_HS_POS) 205 #define RPC_PHYCNT_CKSEL_POS 16 206 #define RPC_PHYCNT_CKSEL (3u << RPC_PHYCNT_CKSEL_POS) 207 #define RPC_PHYCNT_WBUF2_POS 4 208 #define RPC_PHYCNT_WBUF2 (1u << RPC_PHYCNT_WBUF2_POS) 209 #define RPC_PHYCNT_WBUF_POS 2 210 #define RPC_PHYCNT_WBUF (1u << RPC_PHYCNT_WBUF_POS) 211 #define RPC_PHYCNT_PHYMEM_POS 0 212 #define RPC_PHYCNT_PHYMEM (3u << RPC_PHYCNT_PHYMEM_POS) 213 #define RPC_PHYCNT_SDR 0u 214 #define RPC_PHYCNT_DDR 1u 215 #define RPC_PHYCNT_HYPER 3u 216 217 /* PHYOFFSET1 field */ 218 #define RPC_PHYOFFSET1_DDRTMG_POS 28 219 #define RPC_PHYOFFSET1_DDRTMG (7u << RPC_PHYOFFSET1_DDRTMG_POS) 220 #define RPC_PHYOFFSET1_DDR 2u 221 #define RPC_PHYOFFSET1_SDR 3u 222 223 /* PHYOFFSET2 field */ 224 #define RPC_PHYOFFSET2_OCTTMG_POS 8 225 #define RPC_PHYOFFSET2_OCTTMG (7u << RPC_PHYOFFSET2_OCTTMG_POS) 226 #define RPC_PHYOFFSET2_SPI 4u 227 #define RPC_PHYOFFSET2_HYPER 4u 228 #define RPC_PHYOFFSET2_SPI_WBUF 0u 229 #define RPC_PHYOFFSET2_OSPI 3u 230 231 #endif /* RPC_REGISTERS_H */ 232