Searched refs:RPC_BASE (Results 1 – 2 of 2) sorted by relevance
27 mmio_write_32(RPC_BASE + RPC_PHYADJ2, 0xa5390000); in rpc_timing_adjustment()28 mmio_write_32(RPC_BASE + RPC_PHYADJ1, 0x80000000); in rpc_timing_adjustment()29 mmio_write_32(RPC_BASE + RPC_PHYADJ2, 0x00008080); in rpc_timing_adjustment()30 mmio_write_32(RPC_BASE + RPC_PHYADJ1, 0x80000022); in rpc_timing_adjustment()31 mmio_write_32(RPC_BASE + RPC_PHYADJ2, 0x00008080); in rpc_timing_adjustment()32 mmio_write_32(RPC_BASE + RPC_PHYADJ1, 0x80000024); in rpc_timing_adjustment()33 mmio_write_32(RPC_BASE + RPC_PHYADJ2, 0x00000030); in rpc_timing_adjustment()34 mmio_write_32(RPC_BASE + RPC_PHYADJ1, 0x80000032); in rpc_timing_adjustment()
11 #define RPC_BASE 0xEE200000U macro13 #define RPC_BASE 0x10060000U macro18 #define RPC_CMNCR (RPC_BASE + 0x0000U)19 #define RPC_SSLDR (RPC_BASE + 0x0004U)20 #define RPC_DRCR (RPC_BASE + 0x000CU)21 #define RPC_DRCMR (RPC_BASE + 0x0010U)22 #define RPC_DROPR (RPC_BASE + 0x0018U)23 #define RPC_DRENR (RPC_BASE + 0x001CU)24 #define RPC_SMCR (RPC_BASE + 0x0020U)25 #define RPC_SMCMR (RPC_BASE + 0x0024U)[all …]