Searched refs:PMU0IOC_BASE (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/soc/ |
| H A D | soc.c | 88 mmio_write_32(PMU0IOC_BASE + 0x0, 0x00f00020); in system_reset_init()
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| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/ |
| H A D | pmu.c | 1019 ddr_data.gpio0a_iomux_l = mmio_read_32(PMU0IOC_BASE + 0); in pmu_sleep_config()
1020 ddr_data.gpio0a_iomux_h = mmio_read_32(PMU0IOC_BASE + 4); in pmu_sleep_config()
1027 mmio_write_32(PMU0IOC_BASE + 0, in pmu_sleep_config()
1032 mmio_write_32(PMU0IOC_BASE + 0, in pmu_sleep_config()
1036 mmio_write_32(PMU0IOC_BASE + 8, in pmu_sleep_config()
1240 mmio_write_32(PMU0IOC_BASE + 0x4, in pmu_sleep_restore()
1242 mmio_write_32(PMU0IOC_BASE + 0, in pmu_sleep_restore()
1248 ddr_data.gpio0b_iomux_l = mmio_read_32(PMU0IOC_BASE + 0x8); in soc_sleep_config()
1259 mmio_write_32(PMU0IOC_BASE + 0x8, WITH_16BITS_WMSK(ddr_data.gpio0b_iomux_l)); in soc_sleep_restore()
1355 mmio_write_32(PMU0IOC_BASE + 0, BITS_WITH_WMASK(0, 0xf, 8)); in rockchip_soc_system_off()
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| /rk3399_ARM-atf/plat/rockchip/rk3588/ |
| H A D | rk3588_def.h | 51 #define PMU0IOC_BASE 0xfd5f0000 macro
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