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Searched refs:P0 (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/src/
H A Dddrphy_phyinit_progcsrskiptrain.c491 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (P0 | C0 | TINITENG | R2 |
496 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (P0 | C0 | TINITENG | R2 |
501 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (P0 | C0 | TINITENG | R2 |
/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/include/
H A Dddrphy_csr_all_cdefines.h6855 #define P0 0x0U macro