1 /*
2 * Copyright (c) 2021-2026, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdint.h>
9
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <drivers/delay_timer.h>
13 #include <drivers/st/stm32mp1_usb.h>
14 #include <lib/mmio.h>
15
16 #include <platform_def.h>
17
18 #define USB_OTG_MODE_DEVICE 0U
19 #define USB_OTG_MODE_HOST 1U
20 #define USB_OTG_MODE_DRD 2U
21
22 #define EP_TYPE_CTRL 0U
23 #define EP_TYPE_ISOC 1U
24 #define EP_TYPE_BULK 2U
25 #define EP_TYPE_INTR 3U
26
27 #define USBD_FIFO_FLUSH_TIMEOUT_US 1000U
28 #define EP0_FIFO_SIZE 64U
29
30 /* OTG registers offsets */
31 #define OTG_GOTGINT 0x004U
32 #define OTG_GAHBCFG 0x008U
33 #define OTG_GUSBCFG 0x00CU
34 #define OTG_GRSTCTL 0x010U
35 #define OTG_GINTSTS 0x014U
36 #define OTG_GINTMSK 0x018U
37 #define OTG_GRXSTSP 0x020U
38 #define OTG_GGPIO 0x038U
39 #define OTG_GLPMCFG 0x054U
40 #define OTG_DCFG 0x800U
41 #define OTG_DCTL 0x804U
42 #define OTG_DSTS 0x808U
43 #define OTG_DIEPMSK 0x810U
44 #define OTG_DOEPMSK 0x814U
45 #define OTG_DAINT 0x818U
46 #define OTG_DAINTMSK 0x81CU
47 #define OTG_DIEPEMPMSK 0x834U
48
49 /* Definitions for OTG_DIEPx registers */
50 #define OTG_DIEP_BASE 0x900U
51 #define OTG_DIEP_SIZE 0x20U
52 #define OTG_DIEPCTL 0x00U
53 #define OTG_DIEPINT 0x08U
54 #define OTG_DIEPTSIZ 0x10U
55 #define OTG_DIEPDMA 0x14U
56 #define OTG_DTXFSTS 0x18U
57 #define OTG_DIEP_MAX_NB 9U
58
59 /* Definitions for OTG_DOEPx registers */
60 #define OTG_DOEP_BASE 0xB00U
61 #define OTG_DOEP_SIZE 0x20U
62 #define OTG_DOEPCTL 0x00U
63 #define OTG_DOEPINT 0x08U
64 #define OTG_DOEPTSIZ 0x10U
65 #define OTG_DOEPDMA 0x14U
66 #define OTG_D0EP_MAX_NB 9U
67
68 /* Definitions for OTG_DAINT registers */
69 #define OTG_DAINT_OUT_MASK GENMASK(31, 16)
70 #define OTG_DAINT_OUT_SHIFT 16U
71 #define OTG_DAINT_IN_MASK GENMASK(15, 0)
72 #define OTG_DAINT_IN_SHIFT 0U
73
74 #define OTG_DAINT_EP0_IN BIT(16)
75 #define OTG_DAINT_EP0_OUT BIT(0)
76
77 /* Definitions for FIFOs */
78 #define OTG_FIFO_BASE 0x1000U
79 #define OTG_FIFO_SIZE 0x1000U
80
81 /* Bit definitions for OTG_GOTGINT register */
82 #define OTG_GOTGINT_SEDET BIT(2)
83
84 /* Bit definitions for OTG_GAHBCFG register */
85 #define OTG_GAHBCFG_GINT BIT(0)
86
87 /* Bit definitions for OTG_GUSBCFG register */
88 #define OTG_GUSBCFG_TRDT GENMASK(13, 10)
89 #define OTG_GUSBCFG_TRDT_SHIFT 10U
90
91 #define USBD_HS_TRDT_VALUE 9U
92
93 /* Bit definitions for OTG_GRSTCTL register */
94 #define OTG_GRSTCTL_RXFFLSH BIT(4)
95 #define OTG_GRSTCTL_TXFFLSH BIT(5)
96 #define OTG_GRSTCTL_TXFNUM_SHIFT 6U
97
98 /* Bit definitions for OTG_GINTSTS register */
99 #define OTG_GINTSTS_CMOD BIT(0)
100 #define OTG_GINTSTS_MMIS BIT(1)
101 #define OTG_GINTSTS_OTGINT BIT(2)
102 #define OTG_GINTSTS_SOF BIT(3)
103 #define OTG_GINTSTS_RXFLVL BIT(4)
104 #define OTG_GINTSTS_USBSUSP BIT(11)
105 #define OTG_GINTSTS_USBRST BIT(12)
106 #define OTG_GINTSTS_ENUMDNE BIT(13)
107 #define OTG_GINTSTS_IEPINT BIT(18)
108 #define OTG_GINTSTS_OEPINT BIT(19)
109 #define OTG_GINTSTS_IISOIXFR BIT(20)
110 #define OTG_GINTSTS_IPXFR_INCOMPISOOUT BIT(21)
111 #define OTG_GINTSTS_LPMINT BIT(27)
112 #define OTG_GINTSTS_SRQINT BIT(30)
113 #define OTG_GINTSTS_WKUPINT BIT(31)
114
115 /* Bit definitions for OTG_GRXSTSP register */
116 #define OTG_GRXSTSP_EPNUM GENMASK(3, 0)
117 #define OTG_GRXSTSP_BCNT GENMASK(14, 4)
118 #define OTG_GRXSTSP_BCNT_SHIFT 4U
119 #define OTG_GRXSTSP_PKTSTS GENMASK(20, 17)
120 #define OTG_GRXSTSP_PKTSTS_SHIFT 17U
121
122 #define STS_GOUT_NAK 1U
123 #define STS_DATA_UPDT 2U
124 #define STS_XFER_COMP 3U
125 #define STS_SETUP_COMP 4U
126 #define STS_SETUP_UPDT 6U
127
128 /* Bit definitions for OTG_GGPIO register */
129 #define OTG_GGPIO_IDPULLUP_DIS BIT(28)
130
131 /* Bit definitions for OTG_GLPMCFG register */
132 #define OTG_GLPMCFG_BESL GENMASK(5, 2)
133
134 /* Bit definitions for OTG_DCFG register */
135 #define OTG_DCFG_DAD GENMASK(10, 4)
136 #define OTG_DCFG_DAD_SHIFT 4U
137
138 /* Bit definitions for OTG_DCTL register */
139 #define OTG_DCTL_RWUSIG BIT(0)
140 #define OTG_DCTL_SDIS BIT(1)
141 #define OTG_DCTL_CGINAK BIT(8)
142
143 /* Bit definitions for OTG_DSTS register */
144 #define OTG_DSTS_SUSPSTS BIT(0)
145 #define OTG_DSTS_ENUMSPD_MASK GENMASK(2, 1)
146 #define OTG_DSTS_FNSOF0 BIT(8)
147
148 #define OTG_DSTS_ENUMSPD(val) ((val) << 1)
149 #define OTG_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ OTG_DSTS_ENUMSPD(0U)
150 #define OTG_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ OTG_DSTS_ENUMSPD(1U)
151 #define OTG_DSTS_ENUMSPD_LS_PHY_6MHZ OTG_DSTS_ENUMSPD(2U)
152 #define OTG_DSTS_ENUMSPD_FS_PHY_48MHZ OTG_DSTS_ENUMSPD(3U)
153
154 /* Bit definitions for OTG_DIEPMSK register */
155 #define OTG_DIEPMSK_XFRCM BIT(0)
156 #define OTG_DIEPMSK_EPDM BIT(1)
157 #define OTG_DIEPMSK_TOM BIT(3)
158
159 /* Bit definitions for OTG_DOEPMSK register */
160 #define OTG_DOEPMSK_XFRCM BIT(0)
161 #define OTG_DOEPMSK_EPDM BIT(1)
162 #define OTG_DOEPMSK_STUPM BIT(3)
163
164 /* Bit definitions for OTG_DIEPCTLx registers */
165 #define OTG_DIEPCTL_MPSIZ GENMASK(10, 0)
166 #define OTG_DIEPCTL_STALL BIT(21)
167 #define OTG_DIEPCTL_CNAK BIT(26)
168 #define OTG_DIEPCTL_SD0PID_SEVNFRM BIT(28)
169 #define OTG_DIEPCTL_SODDFRM BIT(29)
170 #define OTG_DIEPCTL_EPDIS BIT(30)
171 #define OTG_DIEPCTL_EPENA BIT(31)
172
173 /* Bit definitions for OTG_DIEPINTx registers */
174 #define OTG_DIEPINT_XFRC BIT(0)
175 #define OTG_DIEPINT_EPDISD BIT(1)
176 #define OTG_DIEPINT_TOC BIT(3)
177 #define OTG_DIEPINT_ITTXFE BIT(4)
178 #define OTG_DIEPINT_INEPNE BIT(6)
179 #define OTG_DIEPINT_TXFE BIT(7)
180 #define OTG_DIEPINT_TXFE_SHIFT 7U
181
182 #define OTG_DIEPINT_MASK (BIT(13) | BIT(11) | GENMASK(9, 0))
183
184 /* Bit definitions for OTG_DIEPTSIZx registers */
185 #define OTG_DIEPTSIZ_XFRSIZ GENMASK(18, 0)
186 #define OTG_DIEPTSIZ_PKTCNT GENMASK(28, 19)
187 #define OTG_DIEPTSIZ_PKTCNT_SHIFT 19U
188 #define OTG_DIEPTSIZ_MCNT_MASK GENMASK(30, 29)
189 #define OTG_DIEPTSIZ_MCNT_DATA0 BIT(29)
190
191 #define OTG_DIEPTSIZ_PKTCNT_1 BIT(19)
192
193 /* Bit definitions for OTG_DTXFSTSx registers */
194 #define OTG_DTXFSTS_INEPTFSAV GENMASK(15, 0)
195
196 /* Bit definitions for OTG_DOEPCTLx registers */
197 #define OTG_DOEPCTL_STALL BIT(21)
198 #define OTG_DOEPCTL_CNAK BIT(26)
199 #define OTG_DOEPCTL_SD0PID_SEVNFRM BIT(28) /* other than endpoint 0 */
200 #define OTG_DOEPCTL_SD1PID_SODDFRM BIT(29) /* other than endpoint 0 */
201 #define OTG_DOEPCTL_EPDIS BIT(30)
202 #define OTG_DOEPCTL_EPENA BIT(31)
203
204 /* Bit definitions for OTG_DOEPTSIZx registers */
205 #define OTG_DOEPTSIZ_XFRSIZ GENMASK(18, 0)
206 #define OTG_DOEPTSIZ_PKTCNT GENMASK(28, 19)
207 #define OTG_DOEPTSIZ_RXDPID_STUPCNT GENMASK(30, 29)
208
209 /* Bit definitions for OTG_DOEPINTx registers */
210 #define OTG_DOEPINT_XFRC BIT(0)
211 #define OTG_DOEPINT_STUP BIT(3)
212 #define OTG_DOEPINT_OTEPDIS BIT(4)
213
214 #define OTG_DOEPINT_MASK (GENMASK(15, 12) | GENMASK(9, 8) | GENMASK(6, 0))
215
216 #define EP_NB 15U
217 #define EP_ALL 0x10U
218
219 /*
220 * Flush TX FIFO.
221 * handle: PCD handle.
222 * num: FIFO number.
223 * This parameter can be a value from 1 to 15 or EP_ALL.
224 * EP_ALL= 0x10 means Flush all TX FIFOs
225 * return: USB status.
226 */
usb_dwc2_flush_tx_fifo(void * handle,uint32_t num)227 static enum usb_status usb_dwc2_flush_tx_fifo(void *handle, uint32_t num)
228 {
229 uintptr_t usb_base_addr = (uintptr_t)handle;
230 uint64_t timeout = timeout_init_us(USBD_FIFO_FLUSH_TIMEOUT_US);
231
232 mmio_write_32(usb_base_addr + OTG_GRSTCTL,
233 OTG_GRSTCTL_TXFFLSH | (uint32_t)(num << OTG_GRSTCTL_TXFNUM_SHIFT));
234
235 while ((mmio_read_32(usb_base_addr + OTG_GRSTCTL) &
236 OTG_GRSTCTL_TXFFLSH) == OTG_GRSTCTL_TXFFLSH) {
237 if (timeout_elapsed(timeout)) {
238 return USBD_TIMEOUT;
239 }
240 }
241
242 return USBD_OK;
243 }
244
245 /*
246 * Flush RX FIFO.
247 * handle: PCD handle.
248 * return: USB status.
249 */
usb_dwc2_flush_rx_fifo(void * handle)250 static enum usb_status usb_dwc2_flush_rx_fifo(void *handle)
251 {
252 uintptr_t usb_base_addr = (uintptr_t)handle;
253 uint64_t timeout = timeout_init_us(USBD_FIFO_FLUSH_TIMEOUT_US);
254
255 mmio_write_32(usb_base_addr + OTG_GRSTCTL, OTG_GRSTCTL_RXFFLSH);
256
257 while ((mmio_read_32(usb_base_addr + OTG_GRSTCTL) &
258 OTG_GRSTCTL_RXFFLSH) == OTG_GRSTCTL_RXFFLSH) {
259 if (timeout_elapsed(timeout)) {
260 return USBD_TIMEOUT;
261 }
262 }
263
264 return USBD_OK;
265 }
266
267 /*
268 * Return the global USB interrupt status.
269 * handle: PCD handle.
270 * return: Interrupt register value.
271 */
usb_dwc2_read_int(void * handle)272 static uint32_t usb_dwc2_read_int(void *handle)
273 {
274 uintptr_t usb_base_addr = (uintptr_t)handle;
275
276 return mmio_read_32(usb_base_addr + OTG_GINTSTS) &
277 mmio_read_32(usb_base_addr + OTG_GINTMSK);
278 }
279
280 /*
281 * Return the USB device OUT endpoints interrupt.
282 * handle: PCD handle.
283 * return: Device OUT endpoint interrupts.
284 */
usb_dwc2_all_out_ep_int(void * handle)285 static uint32_t usb_dwc2_all_out_ep_int(void *handle)
286 {
287 uintptr_t usb_base_addr = (uintptr_t)handle;
288
289 return ((mmio_read_32(usb_base_addr + OTG_DAINT) &
290 mmio_read_32(usb_base_addr + OTG_DAINTMSK)) &
291 OTG_DAINT_OUT_MASK) >> OTG_DAINT_OUT_SHIFT;
292 }
293
294 /*
295 * Return the USB device IN endpoints interrupt.
296 * handle: PCD handle.
297 * return: Device IN endpoint interrupts.
298 */
usb_dwc2_all_in_ep_int(void * handle)299 static uint32_t usb_dwc2_all_in_ep_int(void *handle)
300 {
301 uintptr_t usb_base_addr = (uintptr_t)handle;
302
303 return ((mmio_read_32(usb_base_addr + OTG_DAINT) &
304 mmio_read_32(usb_base_addr + OTG_DAINTMSK)) &
305 OTG_DAINT_IN_MASK) >> OTG_DAINT_IN_SHIFT;
306 }
307
308 /*
309 * Return Device OUT EP interrupt register.
310 * handle: PCD handle.
311 * epnum: Endpoint number.
312 * This parameter can be a value from 0 to 15.
313 * return: Device OUT EP Interrupt register.
314 */
usb_dwc2_out_ep_int(void * handle,uint8_t epnum)315 static uint32_t usb_dwc2_out_ep_int(void *handle, uint8_t epnum)
316 {
317 uintptr_t usb_base_addr = (uintptr_t)handle;
318
319 return mmio_read_32(usb_base_addr + OTG_DOEP_BASE +
320 (epnum * OTG_DOEP_SIZE) + OTG_DOEPINT) &
321 mmio_read_32(usb_base_addr + OTG_DOEPMSK);
322 }
323
324 /*
325 * Return Device IN EP interrupt register.
326 * handle: PCD handle.
327 * epnum: Endpoint number.
328 * This parameter can be a value from 0 to 15.
329 * return: Device IN EP Interrupt register.
330 */
usb_dwc2_in_ep_int(void * handle,uint8_t epnum)331 static uint32_t usb_dwc2_in_ep_int(void *handle, uint8_t epnum)
332 {
333 uintptr_t usb_base_addr = (uintptr_t)handle;
334 uint32_t msk;
335 uint32_t emp;
336
337 msk = mmio_read_32(usb_base_addr + OTG_DIEPMSK);
338 emp = mmio_read_32(usb_base_addr + OTG_DIEPEMPMSK);
339 msk |= ((emp >> epnum) << OTG_DIEPINT_TXFE_SHIFT) & OTG_DIEPINT_TXFE;
340
341 return mmio_read_32(usb_base_addr + OTG_DIEP_BASE +
342 (epnum * OTG_DIEP_SIZE) + OTG_DIEPINT) & msk;
343 }
344
345 /*
346 * Return USB core mode.
347 * handle: PCD handle.
348 * return: Core mode.
349 * This parameter can be 0 (host) or 1 (device).
350 */
usb_dwc2_get_mode(void * handle)351 static uint32_t usb_dwc2_get_mode(void *handle)
352 {
353 uintptr_t usb_base_addr = (uintptr_t)handle;
354
355 return mmio_read_32(usb_base_addr + OTG_GINTSTS) & OTG_GINTSTS_CMOD;
356 }
357
358 /*
359 * Activate EP0 for detup transactions.
360 * handle: PCD handle.
361 * return: USB status.
362 */
usb_dwc2_activate_setup(void * handle)363 static enum usb_status usb_dwc2_activate_setup(void *handle)
364 {
365 uintptr_t usb_base_addr = (uintptr_t)handle;
366 uintptr_t reg_offset = usb_base_addr + OTG_DIEP_BASE;
367
368 /* Set the MPS of the IN EP based on the enumeration speed */
369 mmio_clrbits_32(reg_offset + OTG_DIEPCTL, OTG_DIEPCTL_MPSIZ);
370
371 if ((mmio_read_32(usb_base_addr + OTG_DSTS) & OTG_DSTS_ENUMSPD_MASK) ==
372 OTG_DSTS_ENUMSPD_LS_PHY_6MHZ) {
373 mmio_setbits_32(reg_offset + OTG_DIEPCTL, 3U);
374 }
375
376 mmio_setbits_32(usb_base_addr + OTG_DCTL, OTG_DCTL_CGINAK);
377
378 return USBD_OK;
379 }
380
381 /*
382 * Prepare the EP0 to start the first control setup.
383 * handle: Selected device.
384 * return: USB status.
385 */
usb_dwc2_ep0_out_start(void * handle)386 static enum usb_status usb_dwc2_ep0_out_start(void *handle)
387 {
388 uintptr_t usb_base_addr = (uintptr_t)handle;
389 uintptr_t reg_offset = usb_base_addr + OTG_DIEP_BASE + OTG_DIEPTSIZ;
390 uint32_t reg_value = 0U;
391
392 /* PKTCNT = 1 and XFRSIZ = 24 bytes for endpoint 0 */
393 reg_value |= OTG_DIEPTSIZ_PKTCNT_1;
394 reg_value |= (EP0_FIFO_SIZE & OTG_DIEPTSIZ_XFRSIZ);
395 reg_value |= OTG_DOEPTSIZ_RXDPID_STUPCNT;
396
397 mmio_write_32(reg_offset, reg_value);
398
399 return USBD_OK;
400 }
401
402 /*
403 * Write a packet into the TX FIFO associated with the EP/channel.
404 * handle: Selected device.
405 * src: Pointer to source buffer.
406 * ch_ep_num: Endpoint or host channel number.
407 * len: Number of bytes to write.
408 * return: USB status.
409 */
usb_dwc2_write_packet(void * handle,uint8_t * src,uint8_t ch_ep_num,uint16_t len)410 static enum usb_status usb_dwc2_write_packet(void *handle, uint8_t *src,
411 uint8_t ch_ep_num, uint16_t len)
412 {
413 uint32_t reg_offset;
414 uint32_t count32b = (len + 3U) / 4U;
415 uint32_t i;
416
417 reg_offset = (uintptr_t)handle + OTG_FIFO_BASE +
418 (ch_ep_num * OTG_FIFO_SIZE);
419
420 for (i = 0U; i < count32b; i++) {
421 uint32_t src_copy = 0U;
422 uint32_t j;
423
424 /* Data written to FIFO need to be 4 bytes aligned */
425 for (j = 0U; j < 4U; j++) {
426 src_copy += (*(src + j)) << (8U * j);
427 }
428
429 mmio_write_32(reg_offset, src_copy);
430 src += 4U;
431 }
432
433 return USBD_OK;
434 }
435
436 /*
437 * Read a packet from the RX FIFO associated with the EP/channel.
438 * handle: Selected device.
439 * dst: Destination pointer.
440 * len: Number of bytes to read.
441 * return: Pointer to destination buffer.
442 */
usb_dwc2_read_packet(void * handle,uint8_t * dest,uint16_t len)443 static void *usb_dwc2_read_packet(void *handle, uint8_t *dest, uint16_t len)
444 {
445 uint32_t reg_offset;
446 uint32_t count32b = (len + 3U) / 4U;
447 uint32_t i;
448
449 VERBOSE("read packet length %i to 0x%lx\n", len, (uintptr_t)dest);
450
451 reg_offset = (uintptr_t)handle + OTG_FIFO_BASE;
452
453 for (i = 0U; i < count32b; i++) {
454 *(uint32_t *)dest = mmio_read_32(reg_offset);
455 dest += 4U;
456 dsb();
457 }
458
459 return (void *)dest;
460 }
461
462 /*
463 * Setup and start a transfer over an EP.
464 * handle: Selected device
465 * ep: Pointer to endpoint structure.
466 * return: USB status.
467 */
usb_dwc2_ep_start_xfer(void * handle,struct usbd_ep * ep)468 static enum usb_status usb_dwc2_ep_start_xfer(void *handle, struct usbd_ep *ep)
469 {
470 uintptr_t usb_base_addr = (uintptr_t)handle;
471 uint32_t reg_offset;
472 uint32_t reg_value;
473 uint32_t clear_value;
474
475 if (ep->is_in) {
476 reg_offset = usb_base_addr + OTG_DIEP_BASE + (ep->num * OTG_DIEP_SIZE);
477 clear_value = OTG_DIEPTSIZ_PKTCNT | OTG_DIEPTSIZ_XFRSIZ;
478 if (ep->xfer_len == 0U) {
479 reg_value = OTG_DIEPTSIZ_PKTCNT_1;
480 } else {
481 /*
482 * Program the transfer size and packet count
483 * as follows:
484 * xfersize = N * maxpacket + short_packet
485 * pktcnt = N + (short_packet exist ? 1 : 0)
486 */
487 reg_value = (OTG_DIEPTSIZ_PKTCNT &
488 (((ep->xfer_len + ep->maxpacket - 1U) /
489 ep->maxpacket) << OTG_DIEPTSIZ_PKTCNT_SHIFT))
490 | ep->xfer_len;
491
492 if (ep->type == EP_TYPE_ISOC) {
493 clear_value |= OTG_DIEPTSIZ_MCNT_MASK;
494 reg_value |= OTG_DIEPTSIZ_MCNT_DATA0;
495 }
496 }
497
498 mmio_clrsetbits_32(reg_offset + OTG_DIEPTSIZ, clear_value, reg_value);
499
500 if ((ep->type != EP_TYPE_ISOC) && (ep->xfer_len > 0U)) {
501 /* Enable the TX FIFO empty interrupt for this EP */
502 mmio_setbits_32(usb_base_addr + OTG_DIEPEMPMSK, BIT(ep->num));
503 }
504
505 /* EP enable, IN data in FIFO */
506 reg_value = OTG_DIEPCTL_CNAK | OTG_DIEPCTL_EPENA;
507
508 if (ep->type == EP_TYPE_ISOC) {
509 if ((mmio_read_32(usb_base_addr + OTG_DSTS) & OTG_DSTS_FNSOF0) == 0U) {
510 reg_value |= OTG_DIEPCTL_SODDFRM;
511 } else {
512 reg_value |= OTG_DIEPCTL_SD0PID_SEVNFRM;
513 }
514 }
515
516 mmio_setbits_32(reg_offset + OTG_DIEPCTL, reg_value);
517
518 if (ep->type == EP_TYPE_ISOC) {
519 usb_dwc2_write_packet(handle, ep->xfer_buff, ep->num, ep->xfer_len);
520 }
521 } else {
522 reg_offset = usb_base_addr + OTG_DOEP_BASE + (ep->num * OTG_DOEP_SIZE);
523 /*
524 * Program the transfer size and packet count as follows:
525 * pktcnt = N
526 * xfersize = N * maxpacket
527 */
528 if (ep->xfer_len == 0U) {
529 reg_value = ep->maxpacket | OTG_DIEPTSIZ_PKTCNT_1;
530 } else {
531 uint16_t pktcnt = (ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket;
532
533 reg_value = (pktcnt << OTG_DIEPTSIZ_PKTCNT_SHIFT) |
534 (ep->maxpacket * pktcnt);
535 }
536
537 mmio_clrsetbits_32(reg_offset + OTG_DOEPTSIZ,
538 OTG_DOEPTSIZ_XFRSIZ & OTG_DOEPTSIZ_PKTCNT,
539 reg_value);
540
541 /* EP enable */
542 reg_value = OTG_DOEPCTL_CNAK | OTG_DOEPCTL_EPENA;
543
544 if (ep->type == EP_TYPE_ISOC) {
545 if ((mmio_read_32(usb_base_addr + OTG_DSTS) & OTG_DSTS_FNSOF0) == 0U) {
546 reg_value |= OTG_DOEPCTL_SD1PID_SODDFRM;
547 } else {
548 reg_value |= OTG_DOEPCTL_SD0PID_SEVNFRM;
549 }
550 }
551
552 mmio_setbits_32(reg_offset + OTG_DOEPCTL, reg_value);
553 }
554
555 return USBD_OK;
556 }
557
558 /*
559 * Setup and start a transfer over the EP0.
560 * handle: Selected device.
561 * ep: Pointer to endpoint structure.
562 * return: USB status.
563 */
usb_dwc2_ep0_start_xfer(void * handle,struct usbd_ep * ep)564 static enum usb_status usb_dwc2_ep0_start_xfer(void *handle, struct usbd_ep *ep)
565 {
566 uintptr_t usb_base_addr = (uintptr_t)handle;
567 uint32_t reg_offset;
568 uint32_t reg_value;
569
570 if (ep->is_in) {
571 reg_offset = usb_base_addr + OTG_DIEP_BASE +
572 (ep->num * OTG_DIEP_SIZE);
573
574 if (ep->xfer_len == 0U) {
575 reg_value = OTG_DIEPTSIZ_PKTCNT_1;
576 } else {
577 /*
578 * Program the transfer size and packet count
579 * as follows:
580 * xfersize = N * maxpacket + short_packet
581 * pktcnt = N + (short_packet exist ? 1 : 0)
582 */
583
584 if (ep->xfer_len > ep->maxpacket) {
585 ep->xfer_len = ep->maxpacket;
586 }
587
588 reg_value = OTG_DIEPTSIZ_PKTCNT_1 | ep->xfer_len;
589 }
590
591 mmio_clrsetbits_32(reg_offset + OTG_DIEPTSIZ,
592 OTG_DIEPTSIZ_XFRSIZ | OTG_DIEPTSIZ_PKTCNT,
593 reg_value);
594
595 /* Enable the TX FIFO empty interrupt for this EP */
596 if (ep->xfer_len > 0U) {
597 mmio_setbits_32(usb_base_addr + OTG_DIEPEMPMSK,
598 BIT(ep->num));
599 }
600
601 /* EP enable, IN data in FIFO */
602 mmio_setbits_32(reg_offset + OTG_DIEPCTL,
603 OTG_DIEPCTL_CNAK | OTG_DIEPCTL_EPENA);
604 } else {
605 reg_offset = usb_base_addr + OTG_DOEP_BASE +
606 (ep->num * OTG_DOEP_SIZE);
607
608 /*
609 * Program the transfer size and packet count as follows:
610 * pktcnt = N
611 * xfersize = N * maxpacket
612 */
613 if (ep->xfer_len > 0U) {
614 ep->xfer_len = ep->maxpacket;
615 }
616
617 reg_value = OTG_DIEPTSIZ_PKTCNT_1 | ep->maxpacket;
618
619 mmio_clrsetbits_32(reg_offset + OTG_DIEPTSIZ,
620 OTG_DIEPTSIZ_XFRSIZ | OTG_DIEPTSIZ_PKTCNT,
621 reg_value);
622
623 /* EP enable */
624 mmio_setbits_32(reg_offset + OTG_DOEPCTL,
625 OTG_DOEPCTL_CNAK | OTG_DOEPCTL_EPENA);
626 }
627
628 return USBD_OK;
629 }
630
631 /*
632 * Set a stall condition over an EP.
633 * handle: Selected device.
634 * ep: Pointer to endpoint structure.
635 * return: USB status.
636 */
usb_dwc2_ep_set_stall(void * handle,struct usbd_ep * ep)637 static enum usb_status usb_dwc2_ep_set_stall(void *handle, struct usbd_ep *ep)
638 {
639 uintptr_t usb_base_addr = (uintptr_t)handle;
640 uint32_t reg_offset;
641 uint32_t reg_value;
642
643 if (ep->is_in) {
644 reg_offset = usb_base_addr + OTG_DIEP_BASE +
645 (ep->num * OTG_DIEP_SIZE);
646 reg_value = mmio_read_32(reg_offset + OTG_DIEPCTL);
647
648 if ((reg_value & OTG_DIEPCTL_EPENA) == 0U) {
649 reg_value &= ~OTG_DIEPCTL_EPDIS;
650 }
651
652 reg_value |= OTG_DIEPCTL_STALL;
653
654 mmio_write_32(reg_offset + OTG_DIEPCTL, reg_value);
655 } else {
656 reg_offset = usb_base_addr + OTG_DOEP_BASE +
657 (ep->num * OTG_DOEP_SIZE);
658 reg_value = mmio_read_32(reg_offset + OTG_DOEPCTL);
659
660 if ((reg_value & OTG_DOEPCTL_EPENA) == 0U) {
661 reg_value &= ~OTG_DOEPCTL_EPDIS;
662 }
663
664 reg_value |= OTG_DOEPCTL_STALL;
665
666 mmio_write_32(reg_offset + OTG_DOEPCTL, reg_value);
667 }
668
669 return USBD_OK;
670 }
671
672 /*
673 * Stop the USB device mode.
674 * handle: Selected device.
675 * return: USB status.
676 */
usb_dwc2_stop_device(void * handle)677 static enum usb_status usb_dwc2_stop_device(void *handle)
678 {
679 uintptr_t usb_base_addr = (uintptr_t)handle;
680 uint32_t i;
681
682 /* Disable Int */
683 mmio_clrbits_32(usb_base_addr + OTG_GAHBCFG, OTG_GAHBCFG_GINT);
684
685 /* Clear pending interrupts */
686 for (i = 0U; i < EP_NB; i++) {
687 mmio_write_32(usb_base_addr + OTG_DIEP_BASE + (i * OTG_DIEP_SIZE) + OTG_DIEPINT,
688 OTG_DIEPINT_MASK);
689 mmio_write_32(usb_base_addr + OTG_DOEP_BASE + (i * OTG_DOEP_SIZE) + OTG_DOEPINT,
690 OTG_DOEPINT_MASK);
691 }
692
693 mmio_write_32(usb_base_addr + OTG_DAINT, OTG_DAINT_IN_MASK | OTG_DAINT_OUT_MASK);
694
695 /* Clear interrupt masks */
696 mmio_write_32(usb_base_addr + OTG_DIEPMSK, 0U);
697 mmio_write_32(usb_base_addr + OTG_DOEPMSK, 0U);
698 mmio_write_32(usb_base_addr + OTG_DAINTMSK, 0U);
699
700 /* Flush the FIFO */
701 usb_dwc2_flush_rx_fifo(handle);
702 usb_dwc2_flush_tx_fifo(handle, EP_ALL);
703
704 /* Disconnect the USB device by disabling the pull-up/pull-down */
705 mmio_setbits_32((uintptr_t)handle + OTG_DCTL, OTG_DCTL_SDIS);
706
707 #if STM32MP21
708 mmio_clrbits_32(usb_base_addr + OTG_GGPIO, OTG_GGPIO_IDPULLUP_DIS);
709 #endif
710
711 return USBD_OK;
712 }
713
714 /*
715 * Stop the USB device mode.
716 * handle: Selected device.
717 * address: New device address to be assigned.
718 * This parameter can be a value from 0 to 255.
719 * return: USB status.
720 */
usb_dwc2_set_address(void * handle,uint8_t address)721 static enum usb_status usb_dwc2_set_address(void *handle, uint8_t address)
722 {
723 uintptr_t usb_base_addr = (uintptr_t)handle;
724
725 mmio_clrsetbits_32(usb_base_addr + OTG_DCFG,
726 OTG_DCFG_DAD,
727 address << OTG_DCFG_DAD_SHIFT);
728
729 return USBD_OK;
730 }
731
732 /*
733 * Check FIFO for the next packet to be loaded.
734 * handle: Selected device.
735 * epnum : Endpoint number.
736 * xfer_len: Block length.
737 * xfer_count: Number of blocks.
738 * maxpacket: Max packet length.
739 * xfer_buff: Buffer pointer.
740 * return: USB status.
741 */
usb_dwc2_write_empty_tx_fifo(void * handle,uint32_t epnum,uint32_t xfer_len,uint32_t * xfer_count,uint32_t maxpacket,uint8_t ** xfer_buff)742 static enum usb_status usb_dwc2_write_empty_tx_fifo(void *handle,
743 uint32_t epnum,
744 uint32_t xfer_len,
745 uint32_t *xfer_count,
746 uint32_t maxpacket,
747 uint8_t **xfer_buff)
748 {
749 uintptr_t usb_base_addr = (uintptr_t)handle;
750 uint32_t reg_offset;
751 int32_t len;
752 uint32_t len32b;
753 enum usb_status ret;
754
755 len = xfer_len - *xfer_count;
756
757 if ((len > 0) && ((uint32_t)len > maxpacket)) {
758 len = maxpacket;
759 }
760
761 len32b = (len + 3U) / 4U;
762
763 reg_offset = usb_base_addr + OTG_DIEP_BASE + (epnum * OTG_DIEP_SIZE);
764
765 while (((mmio_read_32(reg_offset + OTG_DTXFSTS) &
766 OTG_DTXFSTS_INEPTFSAV) > len32b) &&
767 (*xfer_count < xfer_len) && (xfer_len != 0U)) {
768 /* Write the FIFO */
769 len = xfer_len - *xfer_count;
770
771 if ((len > 0) && ((uint32_t)len > maxpacket)) {
772 len = maxpacket;
773 }
774
775 len32b = (len + 3U) / 4U;
776
777 ret = usb_dwc2_write_packet(handle, *xfer_buff, epnum, len);
778 if (ret != USBD_OK) {
779 return ret;
780 }
781
782 *xfer_buff += len;
783 *xfer_count += len;
784 }
785
786 if (len <= 0) {
787 mmio_clrbits_32(usb_base_addr + OTG_DIEPEMPMSK, BIT(epnum));
788 }
789
790 return USBD_OK;
791 }
792
793 /*
794 * Handle PCD interrupt request.
795 * handle: PCD handle.
796 * param: Pointer to information updated by the IT handling.
797 * return: Action to do after IT handling.
798 */
usb_dwc2_it_handler(void * handle,uint32_t * param)799 static enum usb_action usb_dwc2_it_handler(void *handle, uint32_t *param)
800 {
801 uintptr_t usb_base_addr = (uintptr_t)handle;
802 uint32_t ep_intr;
803 uint32_t epint;
804 uint32_t epnum;
805 uint32_t temp;
806 enum usb_status __unused ret;
807
808 if (usb_dwc2_get_mode(handle) != USB_OTG_MODE_DEVICE) {
809 return USB_NOTHING;
810 }
811
812 /* Avoid spurious interrupt */
813 if (usb_dwc2_read_int(handle) == 0U) {
814 return USB_NOTHING;
815 }
816
817 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_MMIS) != 0U) {
818 /* Incorrect mode, acknowledge the interrupt */
819 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_MMIS);
820 }
821
822 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_OEPINT) != 0U) {
823 uint32_t reg_offset;
824
825 /* Read in the device interrupt bits */
826 ep_intr = usb_dwc2_all_out_ep_int(handle);
827 epnum = 0U;
828 while ((ep_intr & BIT(0)) != BIT(0)) {
829 epnum++;
830 ep_intr >>= 1;
831 }
832
833 reg_offset = usb_base_addr + OTG_DOEP_BASE + (epnum * OTG_DOEP_SIZE) + OTG_DOEPINT;
834
835 epint = usb_dwc2_out_ep_int(handle, epnum);
836
837 if ((epint & OTG_DOEPINT_XFRC) == OTG_DOEPINT_XFRC) {
838 mmio_write_32(reg_offset, OTG_DOEPINT_XFRC);
839 *param = epnum;
840
841 return USB_DATA_OUT;
842 }
843
844 if ((epint & OTG_DOEPINT_STUP) == OTG_DOEPINT_STUP) {
845 /* Inform that a setup packet is available */
846 mmio_write_32(reg_offset, OTG_DOEPINT_STUP);
847
848 return USB_SETUP;
849 }
850
851 if ((epint & OTG_DOEPINT_OTEPDIS) == OTG_DOEPINT_OTEPDIS) {
852 mmio_write_32(reg_offset, OTG_DOEPINT_OTEPDIS);
853 }
854 }
855
856 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_IEPINT) != 0U) {
857 uint32_t reg_offset;
858
859 /* Read in the device interrupt bits */
860 ep_intr = usb_dwc2_all_in_ep_int(handle);
861 epnum = 0U;
862 while ((ep_intr & BIT(0)) != BIT(0)) {
863 epnum++;
864 ep_intr >>= 1;
865 }
866
867 reg_offset = usb_base_addr + OTG_DIEP_BASE + (epnum * OTG_DIEP_SIZE) + OTG_DIEPINT;
868
869 epint = usb_dwc2_in_ep_int(handle, epnum);
870
871 if ((epint & OTG_DIEPINT_XFRC) == OTG_DIEPINT_XFRC) {
872 mmio_clrbits_32(usb_base_addr + OTG_DIEPEMPMSK, BIT(epnum));
873 mmio_write_32(reg_offset, OTG_DIEPINT_XFRC);
874 *param = epnum;
875
876 return USB_DATA_IN;
877 }
878
879 if ((epint & OTG_DIEPINT_TOC) == OTG_DIEPINT_TOC) {
880 mmio_write_32(reg_offset, OTG_DIEPINT_TOC);
881 }
882
883 if ((epint & OTG_DIEPINT_ITTXFE) == OTG_DIEPINT_ITTXFE) {
884 mmio_write_32(reg_offset, OTG_DIEPINT_ITTXFE);
885 }
886
887 if ((epint & OTG_DIEPINT_INEPNE) == OTG_DIEPINT_INEPNE) {
888 mmio_write_32(reg_offset, OTG_DIEPINT_INEPNE);
889 }
890
891 if ((epint & OTG_DIEPINT_EPDISD) == OTG_DIEPINT_EPDISD) {
892 mmio_write_32(reg_offset, OTG_DIEPINT_EPDISD);
893 }
894
895 if ((epint & OTG_DIEPINT_TXFE) == OTG_DIEPINT_TXFE) {
896 *param = epnum;
897
898 return USB_WRITE_EMPTY;
899 }
900 }
901
902 /* Handle resume interrupt */
903 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_WKUPINT) != 0U) {
904 INFO("handle USB : Resume\n");
905
906 /* Clear the remote wake-up signaling */
907 mmio_clrbits_32(usb_base_addr + OTG_DCTL, OTG_DCTL_RWUSIG);
908 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_WKUPINT);
909
910 return USB_RESUME;
911 }
912
913 /* Handle suspend interrupt */
914 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_USBSUSP) != 0U) {
915 INFO("handle USB : Suspend int\n");
916
917 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_USBSUSP);
918
919 if ((mmio_read_32(usb_base_addr + OTG_DSTS) &
920 OTG_DSTS_SUSPSTS) == OTG_DSTS_SUSPSTS) {
921 return USB_SUSPEND;
922 }
923 }
924
925 /* Handle LPM interrupt */
926 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_LPMINT) != 0U) {
927 INFO("handle USB : LPM int enter in suspend\n");
928
929 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_LPMINT);
930 *param = (mmio_read_32(usb_base_addr + OTG_GLPMCFG) &
931 OTG_GLPMCFG_BESL) >> 2;
932
933 return USB_LPM;
934 }
935
936 /* Handle reset interrupt */
937 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_USBRST) != 0U) {
938 INFO("handle USB : Reset\n");
939
940 mmio_clrbits_32(usb_base_addr + OTG_DCTL, OTG_DCTL_RWUSIG);
941
942 usb_dwc2_flush_tx_fifo(handle, 0U);
943
944 mmio_write_32(usb_base_addr + OTG_DAINT, OTG_DAINT_IN_MASK | OTG_DAINT_OUT_MASK);
945 mmio_setbits_32(usb_base_addr + OTG_DAINTMSK, OTG_DAINT_EP0_IN | OTG_DAINT_EP0_OUT);
946
947 mmio_setbits_32(usb_base_addr + OTG_DOEPMSK, OTG_DOEPMSK_STUPM |
948 OTG_DOEPMSK_XFRCM |
949 OTG_DOEPMSK_EPDM);
950 mmio_setbits_32(usb_base_addr + OTG_DIEPMSK, OTG_DIEPMSK_TOM |
951 OTG_DIEPMSK_XFRCM |
952 OTG_DIEPMSK_EPDM);
953
954 /* Set default address to 0 */
955 mmio_clrbits_32(usb_base_addr + OTG_DCFG, OTG_DCFG_DAD);
956
957 /* Setup EP0 to receive SETUP packets */
958 ret = usb_dwc2_ep0_out_start(handle);
959 assert(ret == USBD_OK);
960
961 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_USBRST);
962
963 return USB_RESET;
964 }
965
966 /* Handle enumeration done interrupt */
967 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_ENUMDNE) != 0U) {
968 ret = usb_dwc2_activate_setup(handle);
969 assert(ret == USBD_OK);
970
971 mmio_clrbits_32(usb_base_addr + OTG_GUSBCFG, OTG_GUSBCFG_TRDT);
972
973 mmio_setbits_32(usb_base_addr + OTG_GUSBCFG,
974 (USBD_HS_TRDT_VALUE << OTG_GUSBCFG_TRDT_SHIFT) & OTG_GUSBCFG_TRDT);
975
976 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_ENUMDNE);
977
978 return USB_ENUM_DONE;
979 }
980
981 /* Handle RXQLevel interrupt */
982 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_RXFLVL) != 0U) {
983 mmio_clrbits_32(usb_base_addr + OTG_GINTMSK,
984 OTG_GINTSTS_RXFLVL);
985
986 temp = mmio_read_32(usb_base_addr + OTG_GRXSTSP);
987
988 *param = temp & OTG_GRXSTSP_EPNUM;
989 *param |= (temp & OTG_GRXSTSP_BCNT) << (USBD_OUT_COUNT_SHIFT -
990 OTG_GRXSTSP_BCNT_SHIFT);
991
992 if (((temp & OTG_GRXSTSP_PKTSTS) >> OTG_GRXSTSP_PKTSTS_SHIFT) == STS_DATA_UPDT) {
993 if ((temp & OTG_GRXSTSP_BCNT) != 0U) {
994 mmio_setbits_32(usb_base_addr + OTG_GINTMSK, OTG_GINTSTS_RXFLVL);
995
996 return USB_READ_DATA_PACKET;
997 }
998 } else if (((temp & OTG_GRXSTSP_PKTSTS) >> OTG_GRXSTSP_PKTSTS_SHIFT) ==
999 STS_SETUP_UPDT) {
1000 mmio_setbits_32(usb_base_addr + OTG_GINTMSK, OTG_GINTSTS_RXFLVL);
1001
1002 return USB_READ_SETUP_PACKET;
1003 }
1004
1005 mmio_setbits_32(usb_base_addr + OTG_GINTMSK, OTG_GINTSTS_RXFLVL);
1006 }
1007
1008 /* Handle SOF interrupt */
1009 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_SOF) != 0U) {
1010 INFO("handle USB : SOF\n");
1011
1012 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_SOF);
1013
1014 return USB_SOF;
1015 }
1016
1017 /* Handle incomplete ISO IN interrupt */
1018 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_IISOIXFR) != 0U) {
1019 INFO("handle USB : ISO IN\n");
1020
1021 mmio_write_32(usb_base_addr + OTG_GINTSTS,
1022 OTG_GINTSTS_IISOIXFR);
1023 }
1024
1025 /* Handle incomplete ISO OUT interrupt */
1026 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_IPXFR_INCOMPISOOUT) !=
1027 0U) {
1028 INFO("handle USB : ISO OUT\n");
1029
1030 mmio_write_32(usb_base_addr + OTG_GINTSTS,
1031 OTG_GINTSTS_IPXFR_INCOMPISOOUT);
1032 }
1033
1034 /* Handle connection event interrupt */
1035 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_SRQINT) != 0U) {
1036 INFO("handle USB : Connect\n");
1037
1038 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_SRQINT);
1039 }
1040
1041 /* Handle disconnection event interrupt */
1042 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_OTGINT) != 0U) {
1043 INFO("handle USB : Disconnect\n");
1044
1045 temp = mmio_read_32(usb_base_addr + OTG_GOTGINT);
1046
1047 if ((temp & OTG_GOTGINT_SEDET) == OTG_GOTGINT_SEDET) {
1048 return USB_DISCONNECT;
1049 }
1050 }
1051
1052 return USB_NOTHING;
1053 }
1054
1055 /*
1056 * Start the usb device mode
1057 * usb_core_handle: USB core driver handle.
1058 * return USB status.
1059 */
usb_dwc2_start_device(void * handle)1060 static enum usb_status usb_dwc2_start_device(void *handle)
1061 {
1062 uintptr_t usb_base_addr = (uintptr_t)handle;
1063
1064 mmio_clrbits_32(usb_base_addr + OTG_DCTL, OTG_DCTL_SDIS);
1065 mmio_setbits_32(usb_base_addr + OTG_GAHBCFG, OTG_GAHBCFG_GINT);
1066 #if STM32MP21
1067 mmio_setbits_32(usb_base_addr + OTG_GGPIO, OTG_GGPIO_IDPULLUP_DIS);
1068 #endif
1069 return USBD_OK;
1070 }
1071
1072 static const struct usb_driver usb_dwc2driver = {
1073 .ep0_out_start = usb_dwc2_ep0_out_start,
1074 .ep_start_xfer = usb_dwc2_ep_start_xfer,
1075 .ep0_start_xfer = usb_dwc2_ep0_start_xfer,
1076 .write_packet = usb_dwc2_write_packet,
1077 .read_packet = usb_dwc2_read_packet,
1078 .ep_set_stall = usb_dwc2_ep_set_stall,
1079 .start_device = usb_dwc2_start_device,
1080 .stop_device = usb_dwc2_stop_device,
1081 .set_address = usb_dwc2_set_address,
1082 .write_empty_tx_fifo = usb_dwc2_write_empty_tx_fifo,
1083 .it_handler = usb_dwc2_it_handler
1084 };
1085
1086 /*
1087 * Initialize USB DWC2 driver.
1088 * usb_core_handle: USB core driver handle.
1089 * pcd_handle: PCD handle.
1090 * base_register: USB global register base address.
1091 */
stm32mp1_usb_init_driver(struct usb_handle * usb_core_handle,struct pcd_handle * pcd_handle,void * base_register)1092 void stm32mp1_usb_init_driver(struct usb_handle *usb_core_handle,
1093 struct pcd_handle *pcd_handle,
1094 void *base_register)
1095 {
1096 register_usb_driver(usb_core_handle, pcd_handle, &usb_dwc2driver,
1097 base_register);
1098 }
1099