1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2023-2026, STMicroelectronics - All Rights Reserved 4 */ 5 6 #ifndef _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ 7 #define _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ 8 9 #define CMD_DIV 0 10 #define CMD_MUX 1 11 #define CMD_FLEXGEN 3 12 13 #define CMD_ADDR_BIT 0x80000000 14 15 #define CMD_SHIFT 26 16 #define CMD_MASK 0xFC000000 17 #define CMD_DATA_MASK 0x03FFFFFF 18 19 #define DIV_ID_SHIFT 8 20 #define DIV_ID_MASK 0x0000FF00 21 22 #define DIV_DIVN_SHIFT 0 23 #define DIV_DIVN_MASK 0x000000FF 24 25 #define MUX_ID_SHIFT 4 26 #define MUX_ID_MASK 0x00000FF0 27 28 #define MUX_SEL_SHIFT 0 29 #define MUX_SEL_MASK 0x0000000F 30 31 /* Flexgen define */ 32 #define FLEX_ID_SHIFT 20 33 #define FLEX_SEL_SHIFT 16 34 #define FLEX_PDIV_SHIFT 6 35 #define FLEX_FDIV_SHIFT 0 36 37 #define FLEX_ID_MASK GENMASK_32(25, 20) 38 #define FLEX_SEL_MASK GENMASK_32(19, 16) 39 #define FLEX_PDIV_MASK GENMASK_32(15, 6) 40 #define FLEX_FDIV_MASK GENMASK_32(5, 0) 41 42 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ 43 ((div_id) << DIV_ID_SHIFT |\ 44 (div))) 45 46 #define MUX_CFG(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ 47 ((mux_id) << MUX_ID_SHIFT |\ 48 (sel))) 49 50 #define CLK_ADDR_SHIFT 16 51 #define CLK_ADDR_MASK 0x7FFF0000 52 #define CLK_ADDR_VAL_MASK 0xFFFF 53 54 #define DIV_LSMCU 0 55 #define DIV_APB1 1 56 #define DIV_APB2 2 57 #define DIV_APB3 3 58 #define DIV_APB4 4 59 #define DIV_APBDBG 5 60 #define DIV_RTC 6 61 #define DIV_NB 7 62 63 #define MUX_MUXSEL0 0 64 #define MUX_MUXSEL1 1 65 #define MUX_MUXSEL2 2 66 #define MUX_MUXSEL3 3 67 #define MUX_MUXSEL4 4 68 #define MUX_MUXSEL5 5 69 #define MUX_MUXSEL6 6 70 #define MUX_MUXSEL7 7 71 #define MUX_XBARSEL 8 72 #define MUX_RTC 9 73 #define MUX_MCO1 10 74 #define MUX_MCO2 11 75 #define MUX_ADC12 12 76 #define MUX_ADC3 13 77 #define MUX_USB2PHY1 14 78 #define MUX_USB2PHY2 15 79 #define MUX_USB3PCIEPHY 16 80 #define MUX_DSIBLANE 17 81 #define MUX_DSIPHY 18 82 #define MUX_LVDSPHY 19 83 #define MUX_DTS 20 84 #define MUX_D3PER 21 85 #define MUX_NB 22 86 87 #define MUXSEL_HSI 0 88 #define MUXSEL_HSE 1 89 #define MUXSEL_MSI 2 90 91 /* KERNEL source clocks */ 92 #define MUX_RTC_DISABLED 0x0 93 #define MUX_RTC_LSE 0x1 94 #define MUX_RTC_LSI 0x2 95 #define MUX_RTC_HSE 0x3 96 97 #define MUX_MCO1_FLEX61 0x0 98 #define MUX_MCO1_OBSER0 0x1 99 100 #define MUX_MCO2_FLEX62 0x0 101 #define MUX_MCO2_OBSER1 0x1 102 103 #define MUX_ADC12_FLEX46 0x0 104 #define MUX_ADC12_LSMCU 0x1 105 106 #define MUX_ADC3_FLEX47 0x0 107 #define MUX_ADC3_LSMCU 0x1 108 #define MUX_ADC3_FLEX46 0x2 109 110 #define MUX_USB2PHY1_FLEX57 0x0 111 #define MUX_USB2PHY1_HSE 0x1 112 113 #define MUX_USB2PHY2_FLEX58 0x0 114 #define MUX_USB2PHY2_HSE 0x1 115 116 #define MUX_USB3PCIEPHY_FLEX34 0x0 117 #define MUX_USB3PCIEPHY_HSE 0x1 118 119 #define MUX_DSIBLANE_DSIPHY 0x0 120 #define MUX_DSIBLANE_FLEX27 0x1 121 122 #define MUX_DSIPHY_FLEX28 0x0 123 #define MUX_DSIPHY_HSE 0x1 124 125 #define MUX_LVDSPHY_FLEX32 0x0 126 #define MUX_LVDSPHY_HSE 0x1 127 128 #define MUX_DTS_HSI 0x0 129 #define MUX_DTS_HSE 0x1 130 #define MUX_DTS_MSI 0x2 131 132 #define MUX_D3PER_MSI 0x0 133 #define MUX_D3PER_LSI 0x1 134 #define MUX_D3PER_LSE 0x2 135 136 /* PLLs source clocks */ 137 #define PLL_SRC_HSI 0x0 138 #define PLL_SRC_HSE 0x1 139 #define PLL_SRC_MSI 0x2 140 #define PLL_SRC_DISABLED 0x3 141 142 /* XBAR source clocks */ 143 #define XBAR_SRC_PLL4 0x0 144 #define XBAR_SRC_PLL5 0x1 145 #define XBAR_SRC_PLL6 0x2 146 #define XBAR_SRC_PLL7 0x3 147 #define XBAR_SRC_PLL8 0x4 148 #define XBAR_SRC_HSI 0x5 149 #define XBAR_SRC_HSE 0x6 150 #define XBAR_SRC_MSI 0x7 151 #define XBAR_SRC_HSI_KER 0x8 152 #define XBAR_SRC_HSE_KER 0x9 153 #define XBAR_SRC_MSI_KER 0xA 154 #define XBAR_SRC_SPDIF_SYMB 0xB 155 #define XBAR_SRC_I2S 0xC 156 #define XBAR_SRC_LSI 0xD 157 #define XBAR_SRC_LSE 0xE 158 159 /* 160 * Configure a XBAR channel with its clock source 161 * channel_nb: XBAR channel number from 0 to 63 162 * channel_src: one of the 15 previous XBAR source clocks defines 163 * channel_prediv: value of the PREDIV in channel RCC_PREDIVxCFGR register 164 * can be either 1, 2, 4 or 1024 165 * channel_findiv: value of the FINDIV in channel RCC_FINDIVxCFGR register 166 * from 1 to 64 167 */ 168 169 #define FLEXGEN_CFG(ch, sel, pdiv, fdiv) ((CMD_FLEXGEN << CMD_SHIFT) |\ 170 ((ch) << FLEX_ID_SHIFT) |\ 171 ((sel) << FLEX_SEL_SHIFT) |\ 172 ((pdiv) << FLEX_PDIV_SHIFT) |\ 173 ((fdiv) << FLEX_FDIV_SHIFT)) 174 175 /* Register addresses of MCO1 & MCO2 */ 176 #define MCO1 0x494 177 #define MCO2 0x498 178 179 #define MCO_OFF 0 180 #define MCO_ON 1 181 #define MCO_STATUS_SHIFT 8 182 183 #define MCO_CFG(addr, sel, status) (CMD_ADDR_BIT |\ 184 ((addr) << CLK_ADDR_SHIFT) |\ 185 ((status) << MCO_STATUS_SHIFT) |\ 186 (sel)) 187 188 /* define for st,pll /csg */ 189 #define SSCG_MODE_CENTER_SPREAD 0 190 #define SSCG_MODE_DOWN_SPREAD 1 191 192 /* define for st,drive */ 193 #define LSEDRV_LOWEST 0 194 #define LSEDRV_MEDIUM_LOW 2 195 #define LSEDRV_MEDIUM_HIGH 1 196 #define LSEDRV_HIGHEST 3 197 198 #endif /* _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ */ 199