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Searched refs:MD32PCM_BASE (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_internal.h90 #define MD32PCM_BASE (SPM_BASE + 0x0A00) macro
91 #define MD32PCM_CFGREG_SW_RSTN (MD32PCM_BASE + 0x0000)
92 #define MD32PCM_DMA0_SRC (MD32PCM_BASE + 0x0200)
93 #define MD32PCM_DMA0_DST (MD32PCM_BASE + 0x0204)
94 #define MD32PCM_DMA0_WPPT (MD32PCM_BASE + 0x0208)
95 #define MD32PCM_DMA0_WPTO (MD32PCM_BASE + 0x020C)
96 #define MD32PCM_DMA0_COUNT (MD32PCM_BASE + 0x0210)
97 #define MD32PCM_DMA0_CON (MD32PCM_BASE + 0x0214)
98 #define MD32PCM_DMA0_START (MD32PCM_BASE + 0x0218)
99 #define MD32PCM_DMA0_RLCT (MD32PCM_BASE + 0x0224)
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/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_internal.h38 #define MD32PCM_BASE (SPM_BASE + 0x0A00) macro
39 #define MD32PCM_CFGREG_SW_RSTN (MD32PCM_BASE + 0x0000)
40 #define MD32PCM_DMA0_SRC (MD32PCM_BASE + 0x0200)
41 #define MD32PCM_DMA0_DST (MD32PCM_BASE + 0x0204)
42 #define MD32PCM_DMA0_WPPT (MD32PCM_BASE + 0x0208)
43 #define MD32PCM_DMA0_WPTO (MD32PCM_BASE + 0x020C)
44 #define MD32PCM_DMA0_COUNT (MD32PCM_BASE + 0x0210)
45 #define MD32PCM_DMA0_CON (MD32PCM_BASE + 0x0214)
46 #define MD32PCM_DMA0_START (MD32PCM_BASE + 0x0218)
47 #define MD32PCM_DMA0_RLCT (MD32PCM_BASE + 0x0224)
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/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm_internal.h29 #define MD32PCM_BASE (SPM_BASE + 0x0A00) macro
30 #define MD32PCM_CFGREG_SW_RSTN (MD32PCM_BASE + 0x0000)
31 #define MD32PCM_DMA0_SRC (MD32PCM_BASE + 0x0200)
32 #define MD32PCM_DMA0_DST (MD32PCM_BASE + 0x0204)
33 #define MD32PCM_DMA0_WPPT (MD32PCM_BASE + 0x0208)
34 #define MD32PCM_DMA0_WPTO (MD32PCM_BASE + 0x020C)
35 #define MD32PCM_DMA0_COUNT (MD32PCM_BASE + 0x0210)
36 #define MD32PCM_DMA0_CON (MD32PCM_BASE + 0x0214)
37 #define MD32PCM_DMA0_START (MD32PCM_BASE + 0x0218)
38 #define MD32PCM_DMA0_RLCT (MD32PCM_BASE + 0x0224)
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