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Searched refs:MC_GSC_BASE_HI_MASK (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/nvidia/tegra/drivers/memctrl/
H A Dmemctrl_v2.c195 (uint32_t)(phys_base >> 32) & (uint32_t)MC_GSC_BASE_HI_MASK); in tegra_lock_videomem_nonoverlap()
/rk3399_ARM-atf/plat/nvidia/tegra/include/t186/
H A Dtegra_def.h155 #define MC_GSC_BASE_HI_MASK U(3) macro
/rk3399_ARM-atf/plat/nvidia/tegra/include/t194/
H A Dtegra_def.h92 #define MC_GSC_BASE_HI_MASK U(3) macro