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/rk3399_ARM-atf/plat/arm/board/tc/fdts/
H A Dtc_spmc_common_sp_manifest.dtsi13 * | (63MB) | Trusty (=/=> OP-TEE)
21 * | (11MB) | OP-TEE (=/=> Trusty)
25 * | (2MB) | Firmware Upgrade
27 * | (2MB) | Crypto
29 * | (2MB) | Internal Truested Storage
44 mem_size = <0x200000>; /* 2MB TZC DRAM */
51 mem_size = <0x200000>; /* 2MB TZC DRAM */
58 mem_size = <0xe00000>; /* 14MB TZC DRAM */
H A Dtc_spmc_trusty_sp_manifest.dts15 mem_size = <0x3f00000>; /* 64MB TZC DRAM - 1MB align */
H A Dtc_spmc_optee_sp_manifest.dts15 mem_size = <0xb00000>; /* 11MB TZC DRAM */
/rk3399_ARM-atf/fdts/
H A Dcorstone700_fvp.dts16 * Flash total size: 32 MB
17 * Allocated flash space: 8 MB
H A Dstm32mp157c-lxa-mc1-fw-config.dts6 #define DDR_SIZE 0x20000000 /* 512MB */
H A Dstm32mp157c-lxa-tac-fw-config.dts6 #define DDR_SIZE 0x20000000 /* 512MB */
H A Dstm32mp157d-dk1-fw-config.dts6 #define DDR_SIZE 0x20000000 /* 512MB */
H A Dstm32mp157a-dk1-fw-config.dts6 #define DDR_SIZE 0x20000000 /* 512MB */
H A Dstm32mp157f-dk2-fw-config.dts6 #define DDR_SIZE 0x20000000 /* 512MB */
H A Dstm32mp157c-odyssey-fw-config.dts6 #define DDR_SIZE 0x20000000 /* 512MB */
H A Dstm32mp157c-dk2-fw-config.dts6 #define DDR_SIZE 0x20000000 /* 512MB */
H A Dstm32mp153c-lxa-fairytux2-fw-config.dts6 #define DDR_SIZE 0x20000000 /* 512MB */
H A Dstm32mp157c-dk2-sp_min-fw-config.dts6 #define DDR_SIZE 0x20000000 /* 512MB */
H A Dstm32mp157a-dk1-sp_min-fw-config.dts6 #define DDR_SIZE 0x20000000 /* 512MB */
H A Dstm32mp151a-prtt1a-fw-config.dts6 #define DDR_SIZE 0x10000000 /* 256 MB */
H A Dstm32mp135f-dk-fw-config.dts6 #define DDR_SIZE 0x20000000 /* 512MB */
H A Dn1sdp-single-chip.dts23 * In the first 2GB of DRAM bank the top 16MB are reserved by firmware as secure memory.
H A Dfvp-ve-Cortex-A7x1.dts43 /* 8 MB of designated video RAM */
H A Darm_fpga.dts29 /* Allow to upload a generous 100MB initrd payload. */
/rk3399_ARM-atf/include/plat/marvell/odyssey/csr/
H A Dody-asm.h33 #define MB __asm__ volatile ("dmb sy" : : : "memory") /* Full memory barrier, like MI… macro
/rk3399_ARM-atf/docs/plat/
H A Dnvidia-tegra.rst26 Instruction and 64 KB Data Level 1 caches; and have a 2MB shared Level 2
28 Data Level 1 caches; and also have a 2 MB shared Level 2 unified cache. A
36 instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2
42 dedicated, 128MB main-memory-based optimization cache. After being read
64 48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared
H A Drcar-gen3.rst44 48K/32K, L2$ 2MB
60 HYPERFLASH 64 MB HYPER FLASH (512 MBITS, 160 MHZ, 320 MBYTES/S)
61 QSPI FLASH 16MB QSPI (128 MBITS,80 MHZ,80 MBYTES/S)1 HEADER QSPI
/rk3399_ARM-atf/docs/perf/
H A Dpsci-performance-juno.rst327 because the L2 cache size for the big cluster is lot larger (2MB) compared to
328 the little cluster (1MB).
390 CPUs because the L2 cache size for the big cluster is lot larger (2MB) compared
391 to the little cluster (1MB).
463 CPUs because the L2 cache size for the big cluster is lot larger (2MB) compared
464 to the little cluster (1MB).
/rk3399_ARM-atf/lib/gpt_rme/
H A Dgpt_rme.c210 uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 2MB); in shatter_32mb()
234 uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 32MB); in shatter_512mb()
1468 uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 2MB); in fuse_2mb()
1495 uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 2MB); in check_fuse_32mb()
1526 uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 32MB); in fuse_32mb()
1553 uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 32MB); in check_fuse_512mb()
1584 uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 512MB); in fuse_512mb()
/rk3399_ARM-atf/docs/plat/st/
H A Dstm32mpus.rst56 | default location (end of the first 128MB) is used when absent

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