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Searched refs:MAIN_PLL_MMR_CFG_PLL8_HSDIV_CTRL0 (Results 1 – 1 of 1) sorted by relevance

/rk3399_ARM-atf/plat/ti/k3low/common/
H A Dam62l_bl1_setup.c31 #define MAIN_PLL_MMR_CFG_PLL8_HSDIV_CTRL0 (0x00008080UL) macro
110 mmio_write_32(MAIN_PLL_MMR_BASE + MAIN_PLL_MMR_CFG_PLL8_HSDIV_CTRL0, in bl1_early_platform_setup()
114 mmio_write_32(MAIN_PLL_MMR_BASE + MAIN_PLL_MMR_CFG_PLL8_HSDIV_CTRL0, in bl1_early_platform_setup()