Searched refs:LITCOREGRF_BASE (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/ |
| H A D | pm_pd_regs.c | 178 REG_REGION(0x20, 0x20, 4, LITCOREGRF_BASE, WMSK_VAL),
179 REG_REGION(0x28, 0x30, 4, LITCOREGRF_BASE, WMSK_VAL),
501 mmio_write_32(LITCOREGRF_BASE + 0x30, BITS_WITH_WMASK(1, 0x1, 5)); in pd_dsu_core_restore()
506 mmio_write_32(LITCOREGRF_BASE + 0x30, BITS_WITH_WMASK(0, 0x1, 5)); in pd_dsu_core_restore()
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| /rk3399_ARM-atf/plat/rockchip/rk3588/ |
| H A D | rk3588_def.h | 36 #define LITCOREGRF_BASE 0xfd594000 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/ |
| H A D | rk3588_clk.c | 318 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON2, in clk_cpul_set_rate()
321 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON0_L, in clk_cpul_set_rate()
324 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON0_H, in clk_cpul_set_rate()
327 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON1, in clk_cpul_set_rate()
330 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON0_L, in clk_cpul_set_rate()
333 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON0_L, in clk_cpul_set_rate()
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