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Searched refs:L2 (Results 1 – 10 of 10) sorted by relevance

/rk3399_ARM-atf/plat/nvidia/tegra/include/t194/
H A Dtegra194_ras_private.h79 X(L2, 56, 0x68, "URT Timeout") \
80 X(L2, 55, 0x67, "L2 Protocol Violation") \
81 X(L2, 54, 0x66, "SCF to L2 Slave Error Read") \
82 X(L2, 53, 0x65, "SCF to L2 Slave Error Write") \
83 X(L2, 52, 0x64, "SCF to L2 Decode Error Read") \
84 X(L2, 51, 0x63, "SCF to L2 Decode Error Write") \
85 X(L2, 50, 0x62, "SCF to L2 Request Response Interface Parity Errors") \
86 X(L2, 49, 0x61, "SCF to L2 Advance notice interface parity errors") \
87 X(L2, 48, 0x60, "SCF to L2 Filldata Parity Errors") \
88 X(L2, 47, 0x5F, "SCF to L2 UnCorrectable ECC Data Error on interface") \
[all …]
/rk3399_ARM-atf/fdts/
H A Da5ds.dts30 next-level-cache = <&L2>;
36 next-level-cache = <&L2>;
42 next-level-cache = <&L2>;
48 next-level-cache = <&L2>;
57 L2: cache-controller@1C010000 { label
/rk3399_ARM-atf/docs/perf/
H A Dpsci-performance-juno.rst324 L2 caches are flushed.
327 because the L2 cache size for the big cluster is lot larger (2MB) compared to
387 flush of both L1 and L2 caches.
390 CPUs because the L2 cache size for the big cluster is lot larger (2MB) compared
456 powers down to the cluster level, requiring a flush of both L1 and L2 caches.
463 CPUs because the L2 cache size for the big cluster is lot larger (2MB) compared
/rk3399_ARM-atf/docs/plat/
H A Dnvidia-tegra.rst36 instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2
132 /* L2 ECC parity protection disable flag \*/
149 - 'tegra\_enable\_l2\_ecc\_parity\_prot': This flag enables the L2 ECC and Parity
H A Drz-g2.rst47 ARM CA57 (ARMv8) 1.5 GHz dual core, with NEON/VFPv4, L1$ I/D 48K/32K, L2$ 1MB
48 ARM CA53 (ARMv8) 1.2 GHz quad core, with NEON/VFPv4, L1$ I/D 32K/32K, L2$ 512K
H A Drcar-gen3.rst44 48K/32K, L2$ 2MB
46 L2$ 512K
/rk3399_ARM-atf/docs/plat/nxp/
H A Dnxp-layerscape.rst15 L2/3 packet processing, together with security offload, robust traffic
103 Arm Cortex-A72 cores with ECC-protected L1 and L2 cache memories for high
/rk3399_ARM-atf/docs/design/
H A Dcpu-specific-build-macros.rst1227 cache. The L1 data cache and the L2 unified cache are inclusive. A flush
1228 of the L2 by set/way flushes any dirty lines from the L1 as well. This
/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/include/
H A Dddrphy_csr_all_cdefines.h6806 #define L2 0x200U macro
/rk3399_ARM-atf/docs/
H A Dchange-log.md2674 …- flush L1/L2/L3/Sys cache before HPS cold reset ([7ac7dad](https://review.trustedfirmware.org/plu…
3044 …- adjust H616 L2 cache size in DTB ([ee5b26f](https://review.trustedfirmware.org/plugins/gitiles/T…
4756 …- power on L2 caches for secondary clusters ([c822d26](https://review.trustedfirmware.org/plugins/…
5329 …- flush L2 cache for Cortex-A7/12/15/17 ([c5c160c](https://review.trustedfirmware.org/plugins/giti…
6326 …- disable L2 dataless UniqueClean evictions ([10d5cf1](https://review.trustedfirmware.org/plugins/…
6328 …- set L2 cache data ram latency on A72 cores to 4 cycles ([aee2f33](https://review.trustedfirmware…
6329 …- set L2 cache ECC and and parity on A72 cores ([81858a3](https://review.trustedfirmware.org/plugi…
10674 - arm/a5ds: Add ethernet node and L2 cache node in devicetree
11168 definitions, Allow USE_COHERENT_MEM for K3, Set L2 latency on A72 cores