1 /* 2 * Copyright (C) 2024-2026, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STPMIC2_H 8 #define STPMIC2_H 9 10 #include <drivers/st/stm32_i2c.h> 11 #include <lib/utils_def.h> 12 13 enum { 14 STPMIC2_BUCK1 = 0, 15 STPMIC2_BUCK1H, 16 STPMIC2_BUCK2, 17 STPMIC2_BUCK3, 18 STPMIC2_BUCK4, 19 STPMIC2_BUCK5, 20 STPMIC2_BUCK6, 21 STPMIC2_BUCK7, 22 STPMIC2_REFDDR, 23 STPMIC2_LDO1, 24 STPMIC2_LDO2, 25 STPMIC2_LDO3, 26 STPMIC2_LDO4, 27 STPMIC2_LDO5, 28 STPMIC2_LDO6, 29 STPMIC2_LDO7, 30 STPMIC2_LDO8, 31 STPMIC2_GPO1, 32 STPMIC2_GPO2, 33 STPMIC2_GPO3, 34 STPMIC2_GPO4, 35 STPMIC2_GPO5, 36 STPMIC2_NB_REG 37 }; 38 39 /* Status Registers */ 40 #define PRODUCT_ID 0x00 41 #define VERSION_SR 0x01 42 #define TURN_ON_SR 0x02 43 #define TURN_OFF_SR 0x03 44 #define RESTART_SR 0x04 45 #define OCP_SR1 0x05 46 #define OCP_SR2 0x06 47 #define EN_SR1 0x07 48 #define EN_SR2 0x08 49 #define FS_CNT_SR1 0x09 50 #define FS_CNT_SR2 0x0A 51 #define FS_CNT_SR3 0x0B 52 #define MODE_SR 0x0C 53 /* Control Registers */ 54 #define MAIN_CR 0x10 55 #define VINLOW_CR 0x11 56 #define PKEY_LKP_CR 0x12 57 #define WDG_CR 0x13 58 #define WDG_TMR_CR 0x14 59 #define WDG_TMR_SR 0x15 60 #define FS_OCP_CR1 0x16 61 #define FS_OCP_CR2 0x17 62 #define PADS_PULL_CR 0x18 63 #define BUCKS_PD_CR1 0x19 64 #define BUCKS_PD_CR2 0x1A 65 #define LDOS_PD_CR1 0x1B 66 #define LDOS_PD_CR2 0x1C 67 #define GPO_MRST_CR 0x1C 68 #define BUCKS_MRST_CR 0x1D 69 #define LDOS_MRST_CR 0x1E 70 /* Buck CR */ 71 #define BUCK1_MAIN_CR1 0x20 72 #define BUCK1_MAIN_CR2 0x21 73 #define BUCK1_ALT_CR1 0x22 74 #define BUCK1_ALT_CR2 0x23 75 #define BUCK1_PWRCTRL_CR 0x24 76 #define BUCK2_MAIN_CR1 0x25 77 #define BUCK2_MAIN_CR2 0x26 78 #define BUCK2_ALT_CR1 0x27 79 #define BUCK2_ALT_CR2 0x28 80 #define BUCK2_PWRCTRL_CR 0x29 81 #define BUCK3_MAIN_CR1 0x2A 82 #define BUCK3_MAIN_CR2 0x2B 83 #define BUCK3_ALT_CR1 0x2C 84 #define BUCK3_ALT_CR2 0x2D 85 #define BUCK3_PWRCTRL_CR 0x2E 86 #define BUCK4_MAIN_CR1 0x2F 87 #define BUCK4_MAIN_CR2 0x30 88 #define BUCK4_ALT_CR1 0x31 89 #define BUCK4_ALT_CR2 0x32 90 #define BUCK4_PWRCTRL_CR 0x33 91 #define BUCK5_MAIN_CR1 0x34 92 #define BUCK5_MAIN_CR2 0x35 93 #define BUCK5_ALT_CR1 0x36 94 #define BUCK5_ALT_CR2 0x37 95 #define BUCK5_PWRCTRL_CR 0x38 96 #define BUCK6_MAIN_CR1 0x39 97 #define BUCK6_MAIN_CR2 0x3A 98 #define BUCK6_ALT_CR1 0x3B 99 #define BUCK6_ALT_CR2 0x3C 100 #define BUCK6_PWRCTRL_CR 0x3D 101 #define BUCK7_MAIN_CR1 0x3E 102 #define BUCK7_MAIN_CR2 0x3F 103 #define BUCK7_ALT_CR1 0x40 104 #define BUCK7_ALT_CR2 0x41 105 #define BUCK7_PWRCTRL_CR 0x42 106 /* GPO CR used only on PMIC1L and PMIC2L */ 107 #define GPO1_MAIN_CR 0x43 108 #define GPO1_ALT_CR 0x44 109 #define GPO1_PWRCTRL_CR 0x45 110 #define GPO2_MAIN_CR 0x46 111 #define GPO2_ALT_CR 0x47 112 #define GPO2_PWRCTRL_CR 0x48 113 /* LDO CR */ 114 #define LDO1_MAIN_CR 0x4C 115 #define LDO1_ALT_CR 0x4D 116 #define LDO1_PWRCTRL_CR 0x4E 117 #define LDO2_MAIN_CR 0x4F 118 #define LDO2_ALT_CR 0x50 119 #define LDO2_PWRCTRL_CR 0x51 120 #define LDO3_MAIN_CR 0x52 121 #define LDO3_ALT_CR 0x53 122 #define LDO3_PWRCTRL_CR 0x54 123 #define LDO4_MAIN_CR 0x55 124 #define LDO4_ALT_CR 0x56 125 #define LDO4_PWRCTRL_CR 0x57 126 #define LDO5_MAIN_CR 0x58 127 #define LDO5_ALT_CR 0x59 128 #define LDO5_PWRCTRL_CR 0x5A 129 #define LDO6_MAIN_CR 0x5B 130 #define LDO6_ALT_CR 0x5C 131 #define LDO6_PWRCTRL_CR 0x5D 132 #define LDO7_MAIN_CR 0x5E 133 #define LDO7_ALT_CR 0x5F 134 #define LDO7_PWRCTRL_CR 0x60 135 #define LDO8_MAIN_CR 0x61 136 #define LDO8_ALT_CR 0x62 137 #define LDO8_PWRCTRL_CR 0x63 138 #define REFDDR_MAIN_CR 0x64 139 #define REFDDR_ALT_CR 0x65 140 #define REFDDR_PWRCTRL_CR 0x66 141 /* GPO CR used only on PMIC1L and PMIC2L */ 142 #define GPO3_MAIN_CR 0x67 143 #define GPO3_ALT_CR 0x68 144 #define GPO3_PWRCTRL_CR 0x69 145 #define GPO4_MAIN_CR 0x6A 146 #define GPO4_ALT_CR 0x6B 147 #define GPO4_PWRCTRL_CR 0x6C 148 #define GPO5_MAIN_CR 0x6D 149 #define GPO5_ALT_CR 0x6E 150 #define GPO5_PWRCTRL_CR 0x6F 151 /* INTERRUPT CR */ 152 #define INT_PENDING_R1 0x70 153 #define INT_PENDING_R2 0x71 154 #define INT_PENDING_R3 0x72 155 #define INT_PENDING_R4 0x73 156 #define INT_CLEAR_R1 0x74 157 #define INT_CLEAR_R2 0x75 158 #define INT_CLEAR_R3 0x76 159 #define INT_CLEAR_R4 0x77 160 #define INT_MASK_R1 0x78 161 #define INT_MASK_R2 0x79 162 #define INT_MASK_R3 0x7A 163 #define INT_MASK_R4 0x7B 164 #define INT_SRC_R1 0x7C 165 #define INT_SRC_R2 0x7D 166 #define INT_SRC_R3 0x7E 167 #define INT_SRC_R4 0x7F 168 #define INT_DBG_LATCH_R1 0x80 169 #define INT_DBG_LATCH_R2 0x81 170 #define INT_DBG_LATCH_R3 0x82 171 #define INT_DBG_LATCH_R4 0x83 172 173 /* NVM user control registers */ 174 #define NVM_SR 0x8E 175 #define NVM_CR 0x8F 176 177 /* NVM user shadow registers */ 178 #define NVM_MAIN_CTRL_SHR1 0x90 179 #define NVM_MAIN_CTRL_SHR2 0x91 180 #define NVM_RANK_SHR1 0x92 181 #define NVM_RANK_SHR2 0x93 182 #define NVM_RANK_SHR3 0x94 183 #define NVM_RANK_SHR4 0x95 184 #define NVM_RANK_SHR5 0x96 185 #define NVM_RANK_SHR6 0x97 186 #define NVM_RANK_SHR7 0x98 187 #define NVM_RANK_SHR8 0x99 188 #define NVM_BUCK_MODE_SHR1 0x9A 189 #define NVM_BUCK_MODE_SHR2 0x9B 190 #define NVM_BUCK1_VOUT_SHR 0x9C 191 #define NVM_BUCK2_VOUT_SHR 0x9D 192 #define NVM_BUCK3_VOUT_SHR 0x9E 193 #define NVM_BUCK4_VOUT_SHR 0x9F 194 #define NVM_BUCK5_VOUT_SHR 0xA0 195 #define NVM_BUCK6_VOUT_SHR 0xA1 196 #define NVM_BUCK7_VOUT_SHR 0xA2 197 #define NVM_LDO2_SHR 0xA3 198 #define NVM_LDO3_SHR 0xA4 199 #define NVM_LDO5_SHR 0xA5 200 #define NVM_LDO6_SHR 0xA6 201 #define NVM_LDO7_SHR 0xA7 202 #define NVM_LDO8_SHR 0xA8 203 #define NVM_PD_SHR1 0xA9 204 #define NVM_PD_SHR2 0xAA 205 #define NVM_PD_SHR3 0xAB 206 #define NVM_BUCKS_IOUT_SHR1 0xAC 207 #define NVM_BUCKS_IOUT_SHR2 0xAD 208 #define NVM_LDOS_IOUT_SHR 0xAE 209 #define NVM_FS_OCP_SHR1 0xAF 210 #define NVM_FS_OCP_SHR2 0xB0 211 #define NVM_FS_SHR1 0xB1 212 #define NVM_FS_SHR2 0xB2 213 #define NVM_FS_SHR3 0xB3 214 #define NVM_I2C_ADDR_SHR 0xB5 215 #define NVM_USER_SHR1 0xB6 216 #define NVM_USER_SHR2 0xB7 217 218 /* PRODUCT_ID bits definition */ 219 #define PMIC_NVM_ID_MASK ((uint8_t)GENMASK_32(3, 0)) 220 #define PMIC_NVM_ID_SHIFT 0 221 #define PMIC_REF_ID_MASK ((uint8_t)GENMASK_32(7, 4)) 222 #define PMIC_REF_ID_SHIFT 4 223 #define PMIC_REF_ID_STPMIC1L U(1) 224 #define PMIC_REF_ID_STPMIC25 U(2) 225 #define PMIC_REF_ID_STPMIC2L U(3) 226 227 /* MAIN_CR bits definition */ 228 #define SWOFF BIT(0) 229 230 /* BUCKS_MRST_CR bits definition */ 231 #define BUCK1_MRST BIT(0) 232 #define BUCK2_MRST BIT(1) 233 #define BUCK3_MRST BIT(2) 234 #define BUCK4_MRST BIT(3) 235 #define BUCK5_MRST BIT(4) 236 #define BUCK6_MRST BIT(5) 237 #define BUCK7_MRST BIT(6) 238 #define REFDDR_MRST BIT(7) 239 240 /* LDOS_MRST_CR bits definition */ 241 #define LDO1_MRST BIT(0) 242 #define LDO2_MRST BIT(1) 243 #define LDO3_MRST BIT(2) 244 #define LDO4_MRST BIT(3) 245 #define LDO5_MRST BIT(4) 246 #define LDO6_MRST BIT(5) 247 #define LDO7_MRST BIT(6) 248 #define LDO8_MRST BIT(7) 249 250 /* GPO_MRST_CR bits definition */ 251 #define GPO1_MRST BIT(1) 252 #define GPO2_MRST BIT(2) 253 #define GPO3_MRST BIT(3) 254 #define GPO4_MRST BIT(4) 255 #define GPO5_MRST BIT(5) 256 257 /* LDOx_MAIN_CR */ 258 #define LDO_VOLT_SHIFT 1 259 #define LDO_BYPASS BIT(6) 260 #define LDO1_INPUT_SRC BIT(7) 261 #define LDO3_SNK_SRC BIT(7) 262 #define LDO4_INPUT_SRC_SHIFT 6 263 #define LDO4_INPUT_SRC_MASK GENMASK_32(7, 6) 264 265 /* PWRCTRL register bit definition */ 266 #define PWRCTRL_EN BIT(0) 267 #define PWRCTRL_RS BIT(1) 268 #define PWRCTRL_SEL_SHIFT 2 269 #define PWRCTRL_SEL_MASK GENMASK_32(3, 2) 270 271 /* BUCKx_MAIN_CR2 */ 272 #define PREG_MODE_SHIFT 1 273 #define PREG_MODE_MASK GENMASK_32(2, 1) 274 275 /* BUCKS_PD_CR1 */ 276 #define BUCK1_PD_MASK GENMASK_32(1, 0) 277 #define BUCK2_PD_MASK GENMASK_32(3, 2) 278 #define BUCK3_PD_MASK GENMASK_32(5, 4) 279 #define BUCK4_PD_MASK GENMASK_32(7, 6) 280 281 #define BUCK1_PD_FAST BIT(1) 282 #define BUCK2_PD_FAST BIT(3) 283 #define BUCK3_PD_FAST BIT(5) 284 #define BUCK4_PD_FAST BIT(7) 285 286 /* BUCKS_PD_CR2 */ 287 #define BUCK5_PD_MASK GENMASK_32(1, 0) 288 #define BUCK6_PD_MASK GENMASK_32(3, 2) 289 #define BUCK7_PD_MASK GENMASK_32(5, 4) 290 291 #define BUCK5_PD_FAST BIT(1) 292 #define BUCK6_PD_FAST BIT(3) 293 #define BUCK7_PD_FAST BIT(5) 294 295 /* LDOS_PD_CR1 */ 296 #define LDO1_PD BIT(0) 297 #define LDO2_PD BIT(1) 298 #define LDO3_PD BIT(2) 299 #define LDO4_PD BIT(3) 300 #define LDO5_PD BIT(4) 301 #define LDO6_PD BIT(5) 302 #define LDO7_PD BIT(6) 303 #define LDO8_PD BIT(7) 304 305 /* LDOS_PD_CR2 */ 306 #define REFDDR_PD BIT(0) 307 308 /* FS_OCP_CR1 */ 309 #define FS_OCP_BUCK1 BIT(0) 310 #define FS_OCP_BUCK2 BIT(1) 311 #define FS_OCP_BUCK3 BIT(2) 312 #define FS_OCP_BUCK4 BIT(3) 313 #define FS_OCP_BUCK5 BIT(4) 314 #define FS_OCP_BUCK6 BIT(5) 315 #define FS_OCP_BUCK7 BIT(6) 316 #define FS_OCP_REFDDR BIT(7) 317 318 /* FS_OCP_CR2 */ 319 #define FS_OCP_LDO1 BIT(0) 320 #define FS_OCP_LDO2 BIT(1) 321 #define FS_OCP_LDO3 BIT(2) 322 #define FS_OCP_LDO4 BIT(3) 323 #define FS_OCP_LDO5 BIT(4) 324 #define FS_OCP_LDO6 BIT(5) 325 #define FS_OCP_LDO7 BIT(6) 326 #define FS_OCP_LDO8 BIT(7) 327 328 /* NVM_CR */ 329 #define NVM_CMD_MASK GENMASK_32(1, 0) 330 331 #define NVM_CMD_PROGRAM 1 332 #define NVM_CMD_READ 2 333 334 /* NVM_SR */ 335 #define NVM_BUSY BIT(0) 336 #define NVM_WRITE_FAIL BIT(1) 337 338 /* NVM_BUCK1_VOUT_SHR */ 339 #define BUCK1_VRAN_GE_CFG BIT(7) 340 341 /* IRQ definitions */ 342 #define IT_PONKEY_F 0 343 #define IT_PONKEY_R 1 344 #define IT_BUCK1_OCP 16 345 #define IT_BUCK2_OCP 17 346 #define IT_BUCK3_OCP 18 347 #define IT_BUCK4_OCP 19 348 #define IT_BUCK5_OCP 20 349 #define IT_BUCK6_OCP 21 350 #define IT_BUCK7_OCP 22 351 #define IT_REFDDR_OCP 23 352 #define IT_LDO1_OCP 24 353 #define IT_LDO2_OCP 25 354 #define IT_LDO3_OCP 26 355 #define IT_LDO4_OCP 27 356 #define IT_LDO5_OCP 28 357 #define IT_LDO6_OCP 29 358 #define IT_LDO7_OCP 30 359 #define IT_LDO8_OCP 31 360 361 enum stpmic2_prop_id { 362 STPMIC2_MASK_RESET = 0, 363 STPMIC2_PULL_DOWN, 364 STPMIC2_BYPASS, /* arg: 1=set 0=reset */ 365 STPMIC2_SINK_SOURCE, 366 STPMIC2_OCP, 367 }; 368 369 struct pmic_handle_s { 370 struct i2c_handle_s *i2c_handle; 371 uint32_t i2c_addr; 372 unsigned int pmic_status; 373 uint8_t ref_id; 374 }; 375 376 int stpmic2_register_read(struct pmic_handle_s *pmic, 377 uint8_t register_id, uint8_t *value); 378 int stpmic2_register_write(struct pmic_handle_s *pmic, 379 uint8_t register_id, uint8_t value); 380 int stpmic2_register_update(struct pmic_handle_s *pmic, 381 uint8_t register_id, uint8_t value, uint8_t mask); 382 383 int stpmic2_regulator_set_state(struct pmic_handle_s *pmic, 384 uint8_t id, bool enable); 385 int stpmic2_regulator_get_state(struct pmic_handle_s *pmic, 386 uint8_t id, bool *enabled); 387 388 int stpmic2_regulator_levels_mv(struct pmic_handle_s *pmic, 389 uint8_t id, const uint16_t **levels, 390 size_t *levels_count); 391 int stpmic2_regulator_get_voltage(struct pmic_handle_s *pmic, 392 uint8_t id, uint16_t *val); 393 int stpmic2_regulator_set_voltage(struct pmic_handle_s *pmic, 394 uint8_t id, uint16_t millivolts); 395 396 void stpmic2_dump_regulators(struct pmic_handle_s *pmic); 397 398 int stpmic2_get_version(struct pmic_handle_s *pmic, uint8_t *val); 399 int stpmic2_get_product_id(struct pmic_handle_s *pmic, uint8_t *val); 400 401 int stpmic2_regulator_get_prop(struct pmic_handle_s *pmic, uint8_t id, 402 enum stpmic2_prop_id prop); 403 404 int stpmic2_regulator_set_prop(struct pmic_handle_s *pmic, uint8_t id, 405 enum stpmic2_prop_id prop, uint32_t arg); 406 407 int stpmic2_is_buck1_high_voltage(struct pmic_handle_s *pmic, bool *high); 408 int stpmic2_switch_off(struct pmic_handle_s *pmic); 409 #endif /*STPMIC2_H*/ 410