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Searched refs:GICR_ISENABLER0 (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8183/
H A Dplat_mt_gic.c119 gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0); in mt_gic_rdistif_save()
136 mmio_write_32(gicr_base + GICR_ISENABLER0, gic_data.saved_enable); in mt_gic_rdistif_restore()
/rk3399_ARM-atf/plat/mediatek/drivers/gic600/
H A Dmt_gic_v3.c123 gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0); in mt_gic_rdistif_save()
157 mmio_write_32(gicr_base + GICR_ISENABLER0, gic_data.saved_enable); in mt_gic_rdistif_restore()
183 mmio_write_32(gicr_base + GICR_ISENABLER0, gic_data.saved_enable); in mt_gic_rdistif_restore_all()
/rk3399_ARM-atf/include/drivers/arm/
H A Dgicv3.h172 #define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + U(0x100)) macro
185 #define GICR_ISENABLER GICR_ISENABLER0
/rk3399_ARM-atf/drivers/arm/gic/v3/
H A Dgicv3_private.h560 return mmio_read_32(base + GICR_ISENABLER0); in gicr_read_isenabler0()
565 mmio_write_32(base + GICR_ISENABLER0, val); in gicr_write_isenabler0()