1 /* 2 * Copyright (C) 2022-2026, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #ifndef CLK_STM32_CORE_H 8 #define CLK_STM32_CORE_H 9 10 struct mux_cfg { 11 uint16_t offset; 12 uint8_t shift; 13 uint8_t width; 14 uint8_t bitrdy; 15 }; 16 17 struct gate_cfg { 18 uint16_t offset; 19 uint8_t bit_idx; 20 uint8_t set_clr; 21 }; 22 23 struct clk_div_table { 24 uint16_t val; 25 uint16_t div; 26 }; 27 28 struct div_cfg { 29 const struct clk_div_table *table; 30 uint16_t offset; 31 uint8_t shift; 32 uint8_t width; 33 uint8_t flags; 34 uint8_t bitrdy; 35 }; 36 37 struct parent_cfg { 38 const uint16_t *id_parents; 39 struct mux_cfg *mux; 40 uint8_t num_parents; 41 }; 42 43 struct stm32_clk_priv; 44 45 struct stm32_clk_ops { 46 unsigned long (*recalc_rate)(struct stm32_clk_priv *priv, int id, unsigned long rate); 47 int (*get_parent)(struct stm32_clk_priv *priv, int id); 48 int (*set_rate)(struct stm32_clk_priv *priv, int id, unsigned long rate, 49 unsigned long prate); 50 int (*enable)(struct stm32_clk_priv *priv, int id); 51 void (*disable)(struct stm32_clk_priv *priv, int id); 52 bool (*is_enabled)(struct stm32_clk_priv *priv, int id); 53 void (*init)(struct stm32_clk_priv *priv, int id); 54 }; 55 56 struct clk_stm32 { 57 uint16_t binding; 58 uint16_t parent; 59 uint8_t ops; 60 uint8_t flags; 61 void *clock_cfg; 62 }; 63 64 struct stm32_clk_priv { 65 uintptr_t base; 66 const uint32_t num; 67 const struct clk_stm32 *clks; 68 const struct parent_cfg *parents; 69 const uint32_t nb_parents; 70 const struct gate_cfg *gates; 71 const uint32_t nb_gates; 72 const struct div_cfg *div; 73 const uint32_t nb_div; 74 struct clk_oscillator_data *osci_data; 75 const uint32_t nb_osci_data; 76 uint8_t *gate_refcounts; 77 void *pdata; 78 const struct stm32_clk_ops **ops_array; 79 }; 80 81 struct stm32_clk_bypass { 82 uint16_t offset; 83 uint8_t bit_byp; 84 uint8_t bit_digbyp; 85 }; 86 87 struct stm32_clk_css { 88 uint16_t offset; 89 uint8_t bit_css; 90 }; 91 92 struct stm32_clk_drive { 93 uint16_t offset; 94 uint8_t drv_shift; 95 uint8_t drv_width; 96 uint8_t drv_default; 97 }; 98 99 struct clk_oscillator_data { 100 const char *name; 101 struct stm32_clk_bypass *bypass; 102 struct stm32_clk_css *css; 103 struct stm32_clk_drive *drive; 104 unsigned long frequency; 105 uint16_t id_clk; 106 uint16_t gate_id; 107 uint16_t gate_rdy_id; 108 109 }; 110 111 struct clk_gate_cfg { 112 uint32_t offset; 113 uint8_t bit_idx; 114 }; 115 116 /* CLOCK FLAGS */ 117 #define CLK_IS_CRITICAL BIT(0) 118 #define CLK_IGNORE_UNUSED BIT(1) 119 #define CLK_SET_RATE_PARENT BIT(2) 120 121 #define CLK_DIVIDER_ONE_BASED BIT(0) 122 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) 123 #define CLK_DIVIDER_ALLOW_ZERO BIT(2) 124 #define CLK_DIVIDER_HIWORD_MASK BIT(3) 125 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) 126 #define CLK_DIVIDER_READ_ONLY BIT(5) 127 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) 128 #define CLK_DIVIDER_BIG_ENDIAN BIT(7) 129 130 #define MUX_MAX_PARENTS U(0x8000) 131 #define MUX_PARENT_MASK GENMASK(14, 0) 132 #define MUX_FLAG U(0x8000) 133 #define MUX(mux) ((mux) | MUX_FLAG) 134 135 #define NO_GATE 0 136 #define _NO_ID UINT16_MAX 137 #define CLK_IS_ROOT UINT16_MAX 138 #define MUX_NO_BIT_RDY UINT8_MAX 139 #define DIV_NO_BIT_RDY UINT8_MAX 140 141 #define MASK_WIDTH_SHIFT(_width, _shift) \ 142 GENMASK(((_width) + (_shift) - 1U), (_shift)) 143 144 void clk_stm32_rcc_regs_lock(void); 145 void clk_stm32_rcc_regs_unlock(void); 146 147 int clk_stm32_init(struct stm32_clk_priv *priv, uintptr_t base); 148 void clk_stm32_enable_critical_clocks(void); 149 150 struct stm32_clk_priv *clk_stm32_get_priv(void); 151 152 int clk_get_index(struct stm32_clk_priv *priv, unsigned long binding_id); 153 const struct clk_stm32 *_clk_get(struct stm32_clk_priv *priv, int id); 154 155 int _clk_stm32_gate_wait_ready(struct stm32_clk_priv *priv, uint16_t gate_id, bool ready_on); 156 157 int clk_stm32_get_counter(unsigned long binding_id); 158 159 void _clk_stm32_gate_disable(struct stm32_clk_priv *priv, uint16_t gate_id); 160 int _clk_stm32_gate_enable(struct stm32_clk_priv *priv, uint16_t gate_id); 161 162 int _clk_stm32_set_parent(struct stm32_clk_priv *priv, int id, int src_id); 163 int _clk_stm32_set_parent_by_index(struct stm32_clk_priv *priv, int clk, int sel); 164 165 int _clk_stm32_get_parent(struct stm32_clk_priv *priv, int id); 166 int _clk_stm32_get_parent_by_index(struct stm32_clk_priv *priv, int clk_id, int idx); 167 int _clk_stm32_get_parent_index(struct stm32_clk_priv *priv, int clk_id); 168 169 unsigned long _clk_stm32_get_rate(struct stm32_clk_priv *priv, int id); 170 unsigned long _clk_stm32_get_parent_rate(struct stm32_clk_priv *priv, int id); 171 172 bool _stm32_clk_is_flags(struct stm32_clk_priv *priv, int id, uint8_t flag); 173 174 int _clk_stm32_enable(struct stm32_clk_priv *priv, int id); 175 void _clk_stm32_disable(struct stm32_clk_priv *priv, int id); 176 177 int clk_stm32_enable_call_ops(struct stm32_clk_priv *priv, uint16_t id); 178 void clk_stm32_disable_call_ops(struct stm32_clk_priv *priv, uint16_t id); 179 180 bool _clk_stm32_is_enabled(struct stm32_clk_priv *priv, int id); 181 182 int _clk_stm32_divider_set_rate(struct stm32_clk_priv *priv, int div_id, 183 unsigned long rate, unsigned long parent_rate); 184 185 int clk_stm32_divider_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate, 186 unsigned long prate); 187 188 unsigned long _clk_stm32_divider_recalc(struct stm32_clk_priv *priv, 189 int div_id, 190 unsigned long prate); 191 192 unsigned long clk_stm32_divider_recalc(struct stm32_clk_priv *priv, int idx, 193 unsigned long prate); 194 195 int clk_stm32_gate_enable(struct stm32_clk_priv *priv, int idx); 196 void clk_stm32_gate_disable(struct stm32_clk_priv *priv, int idx); 197 198 bool _clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int gate_id); 199 bool clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int idx); 200 201 uint32_t clk_stm32_div_get_value(struct stm32_clk_priv *priv, int div_id); 202 int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value); 203 int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel); 204 int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t mux_id); 205 206 int stm32_clk_parse_fdt_by_name(void *fdt, int node, const char *name, uint32_t *tab, uint32_t *nb); 207 208 #ifdef CFG_STM32_CLK_DEBUG 209 void clk_stm32_display_clock_info(void); 210 #endif 211 212 struct clk_stm32_div_cfg { 213 uint8_t id; 214 }; 215 216 #define STM32_DIV(idx, _binding, _parent, _flags, _div_id) \ 217 [(idx)] = (struct clk_stm32){ \ 218 .binding = (_binding),\ 219 .parent = (_parent),\ 220 .flags = (_flags),\ 221 .clock_cfg = &(struct clk_stm32_div_cfg){\ 222 .id = (_div_id),\ 223 },\ 224 .ops = STM32_DIVIDER_OPS,\ 225 } 226 227 struct clk_stm32_gate_cfg { 228 uint8_t id; 229 }; 230 231 #define STM32_GATE(idx, _binding, _parent, _flags, _gate_id) \ 232 [(idx)] = (struct clk_stm32){ \ 233 .binding = (_binding),\ 234 .parent = (_parent),\ 235 .flags = (_flags),\ 236 .clock_cfg = &(struct clk_stm32_gate_cfg){\ 237 .id = (_gate_id),\ 238 },\ 239 .ops = STM32_GATE_OPS,\ 240 } 241 242 struct fixed_factor_cfg { 243 uint8_t mult; 244 uint8_t div; 245 }; 246 247 unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv, 248 int _idx, unsigned long prate); 249 250 #define FIXED_FACTOR(idx, _idx, _parent, _mult, _div) \ 251 [(idx)] = (struct clk_stm32){ \ 252 .binding = (_idx),\ 253 .parent = (_parent),\ 254 .clock_cfg = &(struct fixed_factor_cfg){\ 255 .mult = (_mult),\ 256 .div = (_div),\ 257 },\ 258 .ops = FIXED_FACTOR_OPS,\ 259 } 260 261 #define GATE(idx, _binding, _parent, _flags, _offset, _bit_idx) \ 262 [(idx)] = (struct clk_stm32){ \ 263 .binding = (_binding),\ 264 .parent = (_parent),\ 265 .flags = (_flags),\ 266 .clock_cfg = &(struct clk_gate_cfg){\ 267 .offset = (_offset),\ 268 .bit_idx = (_bit_idx),\ 269 },\ 270 .ops = GATE_OPS,\ 271 } 272 273 #define STM32_MUX(idx, _binding, _mux_id, _flags) \ 274 [(idx)] = (struct clk_stm32){ \ 275 .binding = (_binding),\ 276 .parent = (MUX(_mux_id)),\ 277 .flags = (_flags),\ 278 .clock_cfg = NULL,\ 279 .ops = STM32_MUX_OPS\ 280 } 281 282 struct clk_timer_cfg { 283 uint32_t apbdiv; 284 uint32_t timpre; 285 }; 286 287 #define CK_TIMER(idx, _idx, _parent, _flags, _apbdiv, _timpre) \ 288 [(idx)] = (struct clk_stm32){ \ 289 .binding = (_idx),\ 290 .parent = (_parent),\ 291 .flags = (CLK_SET_RATE_PARENT | (_flags)),\ 292 .clock_cfg = &(struct clk_timer_cfg){\ 293 .apbdiv = (_apbdiv),\ 294 .timpre = (_timpre),\ 295 },\ 296 .ops = STM32_TIMER_OPS,\ 297 } 298 299 struct clk_stm32_fixed_rate_cfg { 300 unsigned long rate; 301 }; 302 303 #define CLK_FIXED_RATE(idx, _binding, _rate) \ 304 [(idx)] = (struct clk_stm32){ \ 305 .binding = (_binding),\ 306 .parent = (CLK_IS_ROOT),\ 307 .clock_cfg = &(struct clk_stm32_fixed_rate_cfg){\ 308 .rate = (_rate),\ 309 },\ 310 .ops = STM32_FIXED_RATE_OPS,\ 311 } 312 313 struct clk_oscillator_data *clk_oscillator_get_data(struct stm32_clk_priv *priv, int id); 314 315 struct stm32_osc_cfg { 316 uint8_t osc_id; 317 }; 318 319 extern const struct stm32_clk_ops clk_mux_ops; 320 extern const struct stm32_clk_ops clk_stm32_divider_ops; 321 extern const struct stm32_clk_ops clk_stm32_gate_ops; 322 extern const struct stm32_clk_ops clk_fixed_factor_ops; 323 extern const struct stm32_clk_ops clk_gate_ops; 324 extern const struct stm32_clk_ops clk_timer_ops; 325 extern const struct stm32_clk_ops clk_stm32_fixed_rate_ops; 326 327 enum { 328 NO_OPS, 329 FIXED_FACTOR_OPS, 330 GATE_OPS, 331 STM32_MUX_OPS, 332 STM32_DIVIDER_OPS, 333 STM32_GATE_OPS, 334 STM32_TIMER_OPS, 335 STM32_FIXED_RATE_OPS, 336 337 STM32_LAST_OPS 338 }; 339 340 #endif /* CLK_STM32_CORE_H */ 341