1 /*
2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <arch.h>
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <drivers/arm/cci.h>
14 #include <drivers/arm/ccn.h>
15 #include <drivers/arm/gicv2.h>
16 #include <drivers/arm/sp804_delay_timer.h>
17 #include <drivers/arm/smmu_v3.h>
18 #include <drivers/generic_delay_timer.h>
19 #include <fconf_hw_config_getter.h>
20 #include <lib/mmio.h>
21 #include <lib/smccc.h>
22 #include <lib/xlat_tables/xlat_tables_compat.h>
23 #include <platform_def.h>
24 #include <services/arm_arch_svc.h>
25 #include <services/rmm_core_manifest.h>
26 #if SPM_MM
27 #include <services/spm_mm_partition.h>
28 #endif
29
30 #include <plat/arm/common/arm_config.h>
31 #include <plat/arm/common/plat_arm.h>
32 #include <plat/common/platform.h>
33
34 #include "fvp_private.h"
35
36 /* Defines for GIC Driver build time selection */
37 #define FVP_GICV2 1
38 #define FVP_GICV3 2
39
40 /* Defines for RMM Console */
41 #define FVP_RMM_CONSOLE_BASE UL(0x1c0c0000)
42 #define FVP_RMM_CONSOLE_BAUD UL(115200)
43 #define FVP_RMM_CONSOLE_CLK_IN_HZ UL(14745600)
44 #define FVP_RMM_CONSOLE_NAME "pl011"
45 #define FVP_RMM_CONSOLE_COUNT UL(1)
46
47 /* Defines for RMM PCIe ECAM */
48 #define FVP_RMM_ECAM_BASE PCIE_EXP_BASE
49 #define FVP_RMM_ECAM_SEGMENT UL(0x0)
50 #define FVP_RMM_ECAM_BDF UL(0x0)
51
52 /* Defines for RMM SMMUv3 */
53 #define FVP_RMM_SMMU_BASE PLAT_FVP_SMMUV3_BASE
54 #define FVP_RMM_SMMU_COUNT UL(1)
55
56 /*******************************************************************************
57 * arm_config holds the characteristics of the differences between the three FVP
58 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
59 * at each boot stage by the primary before enabling the MMU (to allow
60 * interconnect configuration) & used thereafter. Each BL will have its own copy
61 * to allow independent operation.
62 ******************************************************************************/
63 arm_config_t arm_config;
64
65 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
66 DEVICE0_SIZE, \
67 MT_DEVICE | MT_RW | EL3_PAS)
68
69 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
70 DEVICE1_SIZE, \
71 MT_DEVICE | MT_RW | EL3_PAS)
72
73 #define MAP_CCN MAP_REGION_FLAT(CCN_BASE, \
74 CCN_SIZE, \
75 MT_DEVICE | MT_RW | MT_SECURE)
76
77 #if FVP_GICR_REGION_PROTECTION
78 #define MAP_GICD_MEM MAP_REGION_FLAT(BASE_GICD_BASE, \
79 BASE_GICD_SIZE, \
80 MT_DEVICE | MT_RW | MT_SECURE)
81
82 /* Map all core's redistributor memory as read-only. After boots up,
83 * per-core map its redistributor memory as read-write */
84 #define MAP_GICR_MEM MAP_REGION_FLAT(BASE_GICR_BASE, \
85 (BASE_GICR_SIZE * PLATFORM_CORE_COUNT),\
86 MT_DEVICE | MT_RO | MT_SECURE)
87 #endif /* FVP_GICR_REGION_PROTECTION */
88
89 /*
90 * Need to be mapped with write permissions in order to set a new non-volatile
91 * counter value.
92 */
93 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
94 DEVICE2_SIZE, \
95 MT_DEVICE | MT_RW | MT_SECURE)
96
97 #if TRANSFER_LIST
98 #ifdef FW_NS_HANDOFF_BASE
99 #define MAP_FW_NS_HANDOFF \
100 MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, PLAT_ARM_FW_HANDOFF_SIZE, \
101 MT_MEMORY | MT_RW | MT_NS)
102 #endif
103 #ifdef PLAT_ARM_EL3_FW_HANDOFF_BASE
104 #define MAP_EL3_FW_HANDOFF \
105 MAP_REGION_FLAT(PLAT_ARM_EL3_FW_HANDOFF_BASE, \
106 PLAT_ARM_FW_HANDOFF_SIZE, MT_MEMORY | MT_RW | EL3_PAS)
107 #endif
108 #endif
109
110 /*
111 * Table of memory regions for various BL stages to map using the MMU.
112 * This doesn't include Trusted SRAM as setup_page_tables() already takes care
113 * of mapping it.
114 */
115 #ifdef IMAGE_BL1
116 const mmap_region_t plat_arm_mmap[] = {
117 ARM_MAP_SHARED_RAM,
118 V2M_MAP_FLASH0_RO,
119 V2M_MAP_IOFPGA,
120 MAP_DEVICE0,
121 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
122 MAP_CCN,
123 #endif
124 #if TRUSTED_BOARD_BOOT
125 /* To access the Root of Trust Public Key registers. */
126 MAP_DEVICE2,
127 /* Map DRAM to authenticate NS_BL2U image. */
128 ARM_MAP_NS_DRAM1,
129 #endif
130 {0}
131 };
132 #endif
133 #ifdef IMAGE_BL2
134 const mmap_region_t plat_arm_mmap[] = {
135 ARM_MAP_SHARED_RAM,
136 V2M_MAP_FLASH0_RW,
137 V2M_MAP_IOFPGA,
138 MAP_DEVICE0,
139 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
140 MAP_CCN,
141 #endif
142 ARM_MAP_NS_DRAM1,
143 #ifdef __aarch64__
144 ARM_MAP_DRAM2,
145 #endif
146 /*
147 * Required to load HW_CONFIG, SPMC and SPs to trusted DRAM.
148 */
149 ARM_MAP_TRUSTED_DRAM,
150
151 /*
152 * Required to load Event Log in TZC secured memory
153 */
154 #if MEASURED_BOOT && (defined(SPD_tspd) || defined(SPD_opteed) || \
155 defined(SPD_spmd))
156 ARM_MAP_EVENT_LOG_DRAM1,
157 #endif /* MEASURED_BOOT && (SPD_tspd || SPD_opteed || SPD_spmd) */
158
159 #if ENABLE_RMM
160 ARM_MAP_RMM_DRAM,
161 #endif /* ENABLE_RMM */
162 #if ENABLE_FEAT_RME
163 ARM_MAP_GPT_L1_DRAM,
164 #endif
165 #ifdef SPD_tspd
166 ARM_MAP_TSP_SEC_MEM,
167 #endif
168 #if TRUSTED_BOARD_BOOT
169 /* To access the Root of Trust Public Key registers. */
170 MAP_DEVICE2,
171 #endif /* TRUSTED_BOARD_BOOT */
172
173 #if CRYPTO_SUPPORT && !RESET_TO_BL2
174 /*
175 * To access shared the Mbed TLS heap while booting the
176 * system with Crypto support
177 */
178 ARM_MAP_BL1_RW,
179 #endif /* CRYPTO_SUPPORT && !RESET_TO_BL2 */
180 #if SPM_MM || SPMC_AT_EL3
181 ARM_SP_IMAGE_MMAP,
182 #endif
183 #if ARM_BL31_IN_DRAM
184 ARM_MAP_BL31_SEC_DRAM,
185 #endif
186 #ifdef SPD_opteed
187 ARM_MAP_OPTEE_CORE_MEM,
188 ARM_OPTEE_PAGEABLE_LOAD_MEM,
189 #endif
190 #ifdef MAP_EL3_FW_HANDOFF
191 MAP_EL3_FW_HANDOFF,
192 #endif
193 { 0 }
194 };
195 #endif
196 #ifdef IMAGE_BL2U
197 const mmap_region_t plat_arm_mmap[] = {
198 MAP_DEVICE0,
199 V2M_MAP_IOFPGA,
200 {0}
201 };
202 #endif
203 #ifdef IMAGE_BL31
204 const mmap_region_t plat_arm_mmap[] = {
205 ARM_MAP_SHARED_RAM,
206 #if USE_DEBUGFS
207 /* Required by devfip, can be removed if devfip is not used */
208 V2M_MAP_FLASH0_RW,
209 #endif /* USE_DEBUGFS */
210 ARM_MAP_EL3_TZC_DRAM,
211 V2M_MAP_IOFPGA,
212 MAP_DEVICE0,
213 #if FVP_GICR_REGION_PROTECTION
214 MAP_GICD_MEM,
215 MAP_GICR_MEM,
216 #else
217 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
218 MAP_CCN,
219 #endif
220 MAP_DEVICE1,
221 #endif /* FVP_GICR_REGION_PROTECTION */
222 ARM_V2M_MAP_MEM_PROTECT,
223 #if SPM_MM
224 ARM_SPM_BUF_EL3_MMAP,
225 #endif
226 #if ENABLE_FEAT_RME
227 ARM_MAP_GPT_L1_DRAM,
228 #endif
229 #if ENABLE_RMM
230 ARM_MAP_EL3_RMM_SHARED_MEM,
231 #endif
232 #ifdef MAP_FW_NS_HANDOFF
233 MAP_FW_NS_HANDOFF,
234 #endif
235 #if defined(MAP_EL3_FW_HANDOFF) && !RESET_TO_BL31
236 MAP_EL3_FW_HANDOFF,
237 #endif
238 { 0 }
239 };
240
241 #if defined(IMAGE_BL31) && SPM_MM
242 const mmap_region_t plat_arm_secure_partition_mmap[] = {
243 V2M_MAP_IOFPGA_EL0, /* for the UART */
244 V2M_MAP_SECURE_SYSTEMREG_EL0, /* for initializing flash */
245 #if PSA_FWU_SUPPORT
246 V2M_MAP_FLASH0_RW_EL0, /* for firmware update service in standalone mm */
247 #endif
248 V2M_MAP_FLASH1_RW_EL0, /* for secure variable service in standalone mm */
249 MAP_REGION_FLAT(DEVICE0_BASE,
250 DEVICE0_SIZE,
251 MT_DEVICE | MT_RO | MT_SECURE | MT_USER),
252 ARM_SP_IMAGE_MMAP,
253 ARM_SP_IMAGE_NS_BUF_MMAP,
254 ARM_SP_IMAGE_RW_MMAP,
255 ARM_SPM_BUF_EL0_MMAP,
256 ARM_SP_PSEUDO_NS_CRB_MMAP,
257 ARM_SP_PSEUDO_S_CRB_MMAP,
258 {0}
259 };
260 #endif
261 #endif
262 #ifdef IMAGE_BL32
263 const mmap_region_t plat_arm_mmap[] = {
264 #ifndef __aarch64__
265 ARM_MAP_SHARED_RAM,
266 ARM_V2M_MAP_MEM_PROTECT,
267 #endif
268 V2M_MAP_IOFPGA,
269 MAP_DEVICE0,
270 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
271 MAP_CCN,
272 #endif
273 MAP_DEVICE1,
274 {0}
275 };
276 #endif
277
278 #ifdef IMAGE_RMM
279 const mmap_region_t plat_arm_mmap[] = {
280 V2M_MAP_IOFPGA,
281 MAP_DEVICE0,
282 MAP_DEVICE1,
283 {0}
284 };
285 #endif
286
287 ARM_CASSERT_MMAP
288
289 #if FVP_INTERCONNECT_DRIVER != FVP_CCN
290 static const int fvp_cci400_map[] = {
291 PLAT_FVP_CCI400_CLUS0_SL_PORT,
292 PLAT_FVP_CCI400_CLUS1_SL_PORT,
293 };
294
295 static const int fvp_cci5xx_map[] = {
296 PLAT_FVP_CCI5XX_CLUS0_SL_PORT,
297 PLAT_FVP_CCI5XX_CLUS1_SL_PORT,
298 };
299
get_interconnect_master(void)300 static unsigned int get_interconnect_master(void)
301 {
302 unsigned int master;
303 u_register_t mpidr;
304
305 mpidr = read_mpidr_el1();
306 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ?
307 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr);
308
309 assert(master < FVP_CLUSTER_COUNT);
310 return master;
311 }
312 #endif
313
314 #if defined(IMAGE_BL31) && SPM_MM
315 /*
316 * Boot information passed to a secure partition during initialisation. Linear
317 * indices in MP information will be filled at runtime.
318 */
319 static spm_mm_mp_info_t sp_mp_info[] = {
320 [0] = {0x80000000, 0},
321 [1] = {0x80000001, 0},
322 [2] = {0x80000002, 0},
323 [3] = {0x80000003, 0},
324 [4] = {0x80000100, 0},
325 [5] = {0x80000101, 0},
326 [6] = {0x80000102, 0},
327 [7] = {0x80000103, 0},
328 };
329
330 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
331 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
332 .h.version = VERSION_1,
333 .h.size = sizeof(spm_mm_boot_info_t),
334 .h.attr = 0,
335 .sp_mem_base = ARM_SP_IMAGE_BASE,
336 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
337 .sp_image_base = ARM_SP_IMAGE_BASE,
338 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
339 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
340 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
341 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
342 .sp_image_size = ARM_SP_IMAGE_SIZE,
343 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
344 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
345 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
346 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
347 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
348 .num_cpus = PLATFORM_CORE_COUNT,
349 .mp_info = &sp_mp_info[0],
350 };
351
plat_get_secure_partition_mmap(void * cookie)352 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
353 {
354 return plat_arm_secure_partition_mmap;
355 }
356
plat_get_secure_partition_boot_info(void * cookie)357 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
358 void *cookie)
359 {
360 return &plat_arm_secure_partition_boot_info;
361 }
362 #endif
363
364 /*******************************************************************************
365 * A single boot loader stack is expected to work on both the Foundation FVP
366 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
367 * SYS_ID register provides a mechanism for detecting the differences between
368 * these platforms. This information is stored in a per-BL array to allow the
369 * code to take the correct path.Per BL platform configuration.
370 ******************************************************************************/
fvp_config_setup(void)371 void __init fvp_config_setup(void)
372 {
373 unsigned int rev, hbi, bld, arch, sys_id;
374
375 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
376 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
377 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
378 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
379 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
380
381 if (arch != ARCH_MODEL) {
382 ERROR("This firmware is for FVP models\n");
383 panic();
384 }
385
386 /*
387 * The build field in the SYS_ID tells which variant of the GIC
388 * memory is implemented by the model.
389 */
390 switch (bld) {
391 case BLD_GIC_VE_MMAP:
392 ERROR("Legacy Versatile Express memory map for GIC peripheral"
393 " is not supported\n");
394 panic();
395 break;
396 case BLD_GIC_A53A57_MMAP:
397 break;
398 default:
399 ERROR("Unsupported board build %x\n", bld);
400 panic();
401 }
402
403 /*
404 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
405 * for the Foundation FVP.
406 */
407 switch (hbi) {
408 case HBI_FOUNDATION_FVP:
409 arm_config.flags = 0;
410
411 /*
412 * Check for supported revisions of Foundation FVP
413 * Allow future revisions to run but emit warning diagnostic
414 */
415 switch (rev) {
416 case REV_FOUNDATION_FVP_V2_0:
417 case REV_FOUNDATION_FVP_V2_1:
418 case REV_FOUNDATION_FVP_v9_1:
419 case REV_FOUNDATION_FVP_v9_6:
420 break;
421 default:
422 WARN("Unrecognized Foundation FVP revision %x\n", rev);
423 break;
424 }
425 break;
426 case HBI_BASE_FVP:
427 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC);
428
429 /*
430 * Check for supported revisions
431 * Allow future revisions to run but emit warning diagnostic
432 */
433 switch (rev) {
434 case REV_BASE_FVP_V0:
435 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400;
436 break;
437 case REV_BASE_FVP_REVC:
438 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 |
439 ARM_CONFIG_FVP_HAS_CCI5XX);
440 break;
441 default:
442 WARN("Unrecognized Base FVP revision %x\n", rev);
443 break;
444 }
445 break;
446 default:
447 ERROR("Unsupported board HBI number 0x%x\n", hbi);
448 panic();
449 }
450
451 /*
452 * We assume that the presence of MT bit, and therefore shifted
453 * affinities, is uniform across the platform: either all CPUs, or no
454 * CPUs implement it.
455 */
456 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U)
457 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
458 }
459
460
fvp_interconnect_init(void)461 void __init fvp_interconnect_init(void)
462 {
463 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
464 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
465 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported");
466 panic();
467 }
468
469 plat_arm_interconnect_init();
470 #else
471 uintptr_t cci_base = 0U;
472 const int *cci_map = NULL;
473 unsigned int map_size = 0U;
474
475 /* Initialize the right interconnect */
476 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) {
477 cci_base = PLAT_FVP_CCI5XX_BASE;
478 cci_map = fvp_cci5xx_map;
479 map_size = ARRAY_SIZE(fvp_cci5xx_map);
480 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) {
481 cci_base = PLAT_FVP_CCI400_BASE;
482 cci_map = fvp_cci400_map;
483 map_size = ARRAY_SIZE(fvp_cci400_map);
484 } else {
485 return;
486 }
487
488 assert(cci_base != 0U);
489 assert(cci_map != NULL);
490 cci_init(cci_base, cci_map, map_size);
491 #endif
492 }
493
fvp_interconnect_enable(void)494 void fvp_interconnect_enable(void)
495 {
496 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
497 plat_arm_interconnect_enter_coherency();
498 #else
499 unsigned int master;
500
501 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
502 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
503 master = get_interconnect_master();
504 cci_enable_snoop_dvm_reqs(master);
505 }
506 #endif
507 }
508
fvp_interconnect_disable(void)509 void fvp_interconnect_disable(void)
510 {
511 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
512 plat_arm_interconnect_exit_coherency();
513 #else
514 unsigned int master;
515
516 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
517 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
518 master = get_interconnect_master();
519 cci_disable_snoop_dvm_reqs(master);
520 }
521 #endif
522 }
523
524 #if CRYPTO_SUPPORT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)525 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
526 {
527 assert(heap_addr != NULL);
528 assert(heap_size != NULL);
529
530 return arm_get_mbedtls_heap(heap_addr, heap_size);
531 }
532 #endif /* CRYPTO_SUPPORT */
533
fvp_timer_init(void)534 void fvp_timer_init(void)
535 {
536 #if USE_SP804_TIMER
537 /* Enable the clock override for SP804 timer 0, which means that no
538 * clock dividers are applied and the raw (35MHz) clock will be used.
539 */
540 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
541
542 /* Initialize delay timer driver using SP804 dual timer 0 */
543 sp804_timer_init(V2M_SP804_TIMER0_BASE,
544 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
545 #else
546 generic_delay_timer_init();
547
548 /* Enable System level generic timer */
549 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
550 CNTCR_FCREQ(0U) | CNTCR_EN);
551 #endif /* USE_SP804_TIMER */
552 }
553
554 /*****************************************************************************
555 * plat_is_smccc_feature_available() - This function checks whether SMCCC
556 * feature is availabile for platform.
557 * @fid: SMCCC function id
558 *
559 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
560 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
561 *****************************************************************************/
plat_is_smccc_feature_available(u_register_t fid)562 int32_t plat_is_smccc_feature_available(u_register_t fid)
563 {
564 switch (fid) {
565 case SMCCC_ARCH_SOC_ID:
566 return SMC_ARCH_CALL_SUCCESS;
567 default:
568 return SMC_ARCH_CALL_NOT_SUPPORTED;
569 }
570 }
571
572 /* Get SOC version */
plat_get_soc_version(void)573 int32_t plat_get_soc_version(void)
574 {
575 return (int32_t)
576 (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE,
577 ARM_SOC_IDENTIFICATION_CODE) |
578 (FVP_SOC_ID & SOC_ID_IMPL_DEF_MASK));
579 }
580
581 /* Get SOC revision */
plat_get_soc_revision(void)582 int32_t plat_get_soc_revision(void)
583 {
584 unsigned int sys_id;
585
586 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
587 return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) &
588 V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK);
589 }
590
591 /* Get SoC name */
plat_get_soc_name(char * soc_name)592 int32_t plat_get_soc_name(char *soc_name)
593 {
594 snprintf(soc_name, SMCCC_SOC_NAME_LEN, "Arm Platform Revision %d",
595 plat_get_soc_revision());
596 return SMC_ARCH_CALL_SUCCESS;
597 }
598 #if ENABLE_RMM
599
600 /* BDF mappings for RP0 RC0 */
601 const struct bdf_mapping_info rc0rp0_bdf_data[] = {
602 /* BDF0 */
603 {0U, /* mapping_base */
604 0x8000U, /* mapping_top */
605 0U, /* mapping_off */
606 0U /* smmu_idx */
607 }
608 };
609
610 /* Root ports for RC0 */
611 const struct root_port_info rc0rp_data[] = {
612 /* RP0 */
613 {0U, /* root_port_id */
614 0U, /* padding */
615 ARRAY_SIZE(rc0rp0_bdf_data), /* num_bdf_mappings */
616 (struct bdf_mapping_info *)rc0rp0_bdf_data /* bdf_mappings */
617 }
618 };
619
620 /* Root complexes */
621 const struct root_complex_info rc_data[] = {
622 /* RC0 */
623 {PCIE_EXP_BASE, /* ecam_base */
624 0U, /* segment */
625 {0U, 0U, 0U}, /* padding */
626 ARRAY_SIZE(rc0rp_data), /* num_root_ports */
627 (struct root_port_info *)rc0rp_data /* root_ports */
628 }
629 };
630
631 /* Number of PCIe Root Complexes */
632 #define FVP_RMM_RC_COUNT ARRAY_SIZE(rc_data)
633
634 /*
635 * Get a pointer to the RMM-EL3 Shared buffer and return it
636 * through the pointer passed as parameter.
637 *
638 * This function returns the size of the shared buffer.
639 */
plat_rmmd_get_el3_rmm_shared_mem(uintptr_t * shared)640 size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared)
641 {
642 *shared = (uintptr_t)RMM_SHARED_BASE;
643
644 return (size_t)RMM_SHARED_SIZE;
645 }
646
647 /*
648 * Calculate checksum of 64-bit words @buffer with @size length
649 */
checksum_calc(uint64_t * buffer,size_t size)650 static uint64_t checksum_calc(uint64_t *buffer, size_t size)
651 {
652 uint64_t sum = 0UL;
653
654 assert(((uintptr_t)buffer & (sizeof(uint64_t) - 1UL)) == 0UL);
655 assert((size & (sizeof(uint64_t) - 1UL)) == 0UL);
656
657 for (unsigned long i = 0UL; i < (size / sizeof(uint64_t)); i++) {
658 sum += buffer[i];
659 }
660
661 return sum;
662 }
663 /*
664 * Boot Manifest v0.5 structure illustration, with two DRAM banks,
665 * a single console and one device memory with two PCIe device
666 * non-coherent address ranges.
667 *
668 * +--------------------------------------------------+
669 * | offset | field | comment |
670 * +--------+--------------------+--------------------+
671 * | 0 | version | 0x00000005 |
672 * +--------+--------------------+--------------------+
673 * | 4 | padding | 0x00000000 |
674 * +--------+--------------------+--------------------+
675 * | 8 | plat_data | NULL |
676 * +--------+--------------------+--------------------+
677 * | 16 | num_banks | |
678 * +--------+--------------------+ |
679 * | 24 | banks | plat_dram +--+
680 * +--------+--------------------+ | |
681 * | 32 | checksum | | |
682 * +--------+--------------------+--------------------+ |
683 * | 40 | num_consoles | | |
684 * +--------+--------------------+ | |
685 * | 48 | consoles | plat_console +--|--+
686 * +--------+--------------------+ | | |
687 * | 56 | checksum | | | |
688 * +--------+--------------------+--------------------+ | |
689 * | 64 | num_banks | | | |
690 * +--------+--------------------+ | | |
691 * | 72 | banks | plat_ncoh_region +--|--|--+
692 * +--------+--------------------+ | | | |
693 * | 80 | checksum | | | | |
694 * +--------+--------------------+--------------------+ | | |
695 * | 88 | num_banks | | | | |
696 * +--------+--------------------+ | | | |
697 * | 96 | banks | plat_coh_region | | | |
698 * +--------+--------------------+ | | | |
699 * | 104 | checksum | | | | |
700 * +--------+--------------------+--------------------+ | | |
701 * | 112 | num_smmus | | | | |
702 * +--------+--------------------+ | | | |
703 * | 120 | smmus | plat_smmu +--|--|--|--+
704 * +--------+--------------------+ | | | | |
705 * | 128 | checksum | | | | | |
706 * +--------+--------------------+--------------------+ | | | |
707 * | 136 | num_root_complex | | | | | |
708 * +--------+--------------------+ | | | | |
709 * | 144 | rc_info_version | | | | | |
710 * +--------+--------------------+ | | | | |
711 * | 148 | padding | plat_root_complex +--|--|--|--|--+
712 * +--------+--------------------+ | | | | | |
713 * | 152 | root_complex | | | | | | |
714 * +--------+--------------------+ | | | | | |
715 * | 160 | checksum | | | | | | |
716 * +--------+--------------------+--------------------+<-+ | | | |
717 * | 168 | base 0 | | | | | |
718 * +--------+--------------------+ mem_bank[0] | | | | |
719 * | 176 | size 0 | | | | | |
720 * +--------+--------------------+--------------------+ | | | |
721 * | 184 | base 1 | | | | | |
722 * +--------+--------------------+ mem_bank[1] | | | | |
723 * | 192 | size 1 | | | | | |
724 * +--------+--------------------+--------------------+<----+ | | |
725 * | 200 | base | | | | |
726 * +--------+--------------------+ | | | |
727 * | 208 | map_pages | | | | |
728 * +--------+--------------------+ | | | |
729 * | 216 | name | | | | |
730 * +--------+--------------------+ consoles[0] | | | |
731 * | 224 | clk_in_hz | | | | |
732 * +--------+--------------------+ | | | |
733 * | 232 | baud_rate | | | | |
734 * +--------+--------------------+ | | | |
735 * | 240 | flags | | | | |
736 * +--------+--------------------+--------------------+<-------+ | |
737 * | 248 | base 0 | | | |
738 * +--------+--------------------+ ncoh_region[0] | | |
739 * | 256 | size 0 | | | |
740 * +--------+--------------------+--------------------+ | |
741 * | 264 | base 1 | | | |
742 * +--------+--------------------+ ncoh_region[1] | | |
743 * | 272 | size 1 | | | |
744 * +--------+--------------------+--------------------+<----------+ |
745 * | 280 | smmu_base | | |
746 * +--------+--------------------+ smmus[0] | |
747 * | 288 | smmu_r_base | | |
748 * +--------+--------------------+--------------------+<-------------+
749 * | 296 | ecam_base | |
750 * +--------+--------------------+ |
751 * | 304 | segment | |
752 * +--------+--------------------+ |
753 * | 305 | padding | root_complex[0] +--+
754 * +--------+--------------------+ | |
755 * | 308 | num_root_ports | | |
756 * +--------+--------------------+ | |
757 * | 312 | root_ports | | |
758 * +--------+--------------------+--------------------+<-+
759 * | 320 | root_port_id | |
760 * +--------+--------------------+ |
761 * | 322 | padding | |
762 * +--------+--------------------+ root_ports[0] +--+
763 * | 324 | num_bdf_mappings | | |
764 * +--------+--------------------+ | |
765 * | 328 | bdf_mappings | | |
766 * +--------+--------------------+--------------------+<-+
767 * | 336 | mapping_base | |
768 * +--------+--------------------+ |
769 * | 338 | mapping_top | |
770 * +--------+--------------------+ bdf_mappings[0] |
771 * | 340 | mapping_off | |
772 * +--------+--------------------+ |
773 * | 342 | smmu_idx | |
774 * +--------+--------------------+--------------------+
775 */
plat_rmmd_load_manifest(struct rmm_manifest * manifest)776 int plat_rmmd_load_manifest(struct rmm_manifest *manifest)
777 {
778 uint64_t checksum, num_banks, num_consoles;
779 uint64_t num_ncoh_regions, num_coh_regions;
780 uint64_t num_smmus, num_root_complex;
781 unsigned int num_root_ports, num_bdf_mappings;
782 uint32_t o_realm;
783 struct memory_bank *bank_ptr, *ncoh_region_ptr, *coh_region_ptr;
784 struct console_info *console_ptr;
785 struct smmu_info *smmu_ptr;
786 struct root_complex_info *root_complex_ptr, *rc_ptr;
787 struct root_port_info *root_port_ptr, *rp_ptr;
788 struct bdf_mapping_info *bdf_mapping_ptr, *bdf_ptr;
789
790 assert(manifest != NULL);
791
792 /* Get number of DRAM banks */
793 num_banks = FCONF_GET_PROPERTY(hw_config, dram_layout, num_banks);
794 assert(num_banks <= ARM_DRAM_NUM_BANKS);
795
796 /* Set number of consoles */
797 num_consoles = FVP_RMM_CONSOLE_COUNT;
798
799 /* Set number of device non-coherent address ranges for FVP RevC */
800 num_ncoh_regions = 2;
801
802 /* Set number of SMMUs */
803 num_smmus = FVP_RMM_SMMU_COUNT;
804
805 /* Set number of PCIe root complexes */
806 num_root_complex = FVP_RMM_RC_COUNT;
807
808 /* Calculate and set number of all PCIe root ports and BDF mappings */
809 num_root_ports = 0U;
810 num_bdf_mappings = 0U;
811
812 /* Scan all root complex entries */
813 for (unsigned long i = 0UL; i < num_root_complex; i++) {
814 num_root_ports += rc_data[i].num_root_ports;
815
816 /* Scan all root ports entries in root complex */
817 for (unsigned int j = 0U; j < rc_data[i].num_root_ports; j++) {
818 num_bdf_mappings += rc_data[i].root_ports[j].num_bdf_mappings;
819 }
820 }
821
822 manifest->version = RMMD_MANIFEST_VERSION;
823 manifest->padding = 0U; /* RES0 */
824 manifest->plat_data = 0UL;
825 manifest->plat_dram.num_banks = num_banks;
826 manifest->plat_console.num_consoles = num_consoles;
827 manifest->plat_ncoh_region.num_banks = num_ncoh_regions;
828 manifest->plat_smmu.num_smmus = num_smmus;
829 manifest->plat_root_complex.num_root_complex = num_root_complex;
830 manifest->plat_root_complex.rc_info_version = PCIE_RC_INFO_VERSION;
831 manifest->plat_root_complex.padding = 0U; /* RES0 */
832
833 /* FVP does not support device coherent address ranges */
834 num_coh_regions = 0UL;
835 manifest->plat_coh_region.num_banks = num_coh_regions;
836 manifest->plat_coh_region.banks = NULL;
837 manifest->plat_coh_region.checksum = 0UL;
838
839 bank_ptr = (struct memory_bank *)
840 (((uintptr_t)manifest) + sizeof(struct rmm_manifest));
841 console_ptr = (struct console_info *)
842 ((uintptr_t)bank_ptr + (num_banks *
843 sizeof(struct memory_bank)));
844 ncoh_region_ptr = (struct memory_bank *)
845 ((uintptr_t)console_ptr + (num_consoles *
846 sizeof(struct console_info)));
847 coh_region_ptr = (struct memory_bank *)
848 ((uintptr_t)ncoh_region_ptr + (num_ncoh_regions *
849 sizeof(struct memory_bank)));
850 smmu_ptr = (struct smmu_info *)
851 ((uintptr_t)coh_region_ptr + (num_coh_regions *
852 sizeof(struct memory_bank)));
853 root_complex_ptr = (struct root_complex_info *)
854 ((uintptr_t)smmu_ptr + (num_smmus *
855 sizeof(struct smmu_info)));
856 root_port_ptr = (struct root_port_info *)
857 ((uintptr_t)root_complex_ptr + (num_root_complex *
858 sizeof(struct root_complex_info)));
859 bdf_mapping_ptr = (struct bdf_mapping_info *)
860 ((uintptr_t)root_port_ptr + (num_root_ports *
861 sizeof(struct root_port_info)));
862
863 manifest->plat_dram.banks = bank_ptr;
864 manifest->plat_console.consoles = console_ptr;
865 manifest->plat_ncoh_region.banks = ncoh_region_ptr;
866 manifest->plat_smmu.smmus = smmu_ptr;
867 manifest->plat_root_complex.root_complex = root_complex_ptr;
868
869 /* Ensure the manifest is not larger than the shared buffer */
870 assert((sizeof(struct rmm_manifest) +
871 (sizeof(struct memory_bank) *
872 manifest->plat_dram.num_banks) +
873 (sizeof(struct console_info) *
874 manifest->plat_console.num_consoles) +
875 (sizeof(struct memory_bank) *
876 manifest->plat_ncoh_region.num_banks) +
877 (sizeof(struct memory_bank) *
878 manifest->plat_coh_region.num_banks) +
879 (sizeof(struct smmu_info) *
880 manifest->plat_smmu.num_smmus) +
881 (sizeof(struct root_complex_info) *
882 manifest->plat_root_complex.num_root_complex) +
883 (sizeof(struct root_port_info) * num_root_ports) +
884 (sizeof(struct bdf_mapping_info) * num_bdf_mappings))
885 <= ARM_EL3_RMM_SHARED_SIZE);
886
887 /* Calculate checksum of plat_dram structure */
888 checksum = num_banks + (uint64_t)bank_ptr;
889
890 /* Store FVP DRAM banks data in Boot Manifest */
891 for (unsigned long i = 0UL; i < num_banks; i++) {
892 bank_ptr[i].base = FCONF_GET_PROPERTY(hw_config, dram_layout, dram_bank[i].base);
893 bank_ptr[i].size = FCONF_GET_PROPERTY(hw_config, dram_layout, dram_bank[i].size);
894 }
895
896 /* Update checksum */
897 checksum += checksum_calc((uint64_t *)bank_ptr, sizeof(struct memory_bank) * num_banks);
898
899 /* Checksum must be 0 */
900 manifest->plat_dram.checksum = ~checksum + 1UL;
901
902 /* Calculate the checksum of plat_consoles structure */
903 checksum = num_consoles + (uint64_t)console_ptr;
904
905 /* Zero out the console info struct */
906 (void)memset((void *)console_ptr, '\0',
907 sizeof(struct console_info) * num_consoles);
908
909 console_ptr[0].base = FVP_RMM_CONSOLE_BASE;
910 console_ptr[0].map_pages = 1UL;
911 console_ptr[0].clk_in_hz = FVP_RMM_CONSOLE_CLK_IN_HZ;
912 console_ptr[0].baud_rate = FVP_RMM_CONSOLE_BAUD;
913
914 (void)strlcpy(console_ptr[0].name, FVP_RMM_CONSOLE_NAME,
915 RMM_CONSOLE_MAX_NAME_LEN - 1UL);
916
917 /* Update checksum */
918 checksum += checksum_calc((uint64_t *)console_ptr,
919 sizeof(struct console_info) * num_consoles);
920 /* Checksum must be 0 */
921 manifest->plat_console.checksum = ~checksum + 1UL;
922
923 /*
924 * Calculate the checksum of device non-coherent address ranges
925 * info structure
926 */
927 checksum = num_ncoh_regions + (uint64_t)ncoh_region_ptr;
928
929 /* Zero out the PCIe region info struct */
930 (void)memset((void *)ncoh_region_ptr, 0,
931 sizeof(struct memory_bank) * num_ncoh_regions);
932
933 /* Set number of device non-coherent address ranges based on DT */
934 num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions);
935
936 for (unsigned long i = 0UL; i < num_ncoh_regions; i++) {
937 ncoh_region_ptr[i].base =
938 FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].base);
939 ncoh_region_ptr[i].size =
940 FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].size);
941 }
942
943 /*
944 * Workaround if the DT does not specify the 2nd PCIe region. This code can be
945 * removed when upstream DT is updated to have 2nd PCIe region.
946 */
947 if (num_ncoh_regions == 1) {
948 num_ncoh_regions++;
949 /* Add 3GB of 2nd PCIe region */
950 ncoh_region_ptr[1].base = 0x4000000000;
951 ncoh_region_ptr[1].size = 0xc0000000;
952 }
953
954 /* Update checksum */
955 checksum += checksum_calc((uint64_t *)ncoh_region_ptr,
956 sizeof(struct memory_bank) * num_ncoh_regions);
957
958 /* Checksum must be 0 */
959 manifest->plat_ncoh_region.checksum = ~checksum + 1UL;
960
961 /* Calculate the checksum of the plat_smmu structure */
962 checksum = num_smmus + (uint64_t)smmu_ptr;
963
964 smmu_ptr[0].smmu_base = FVP_RMM_SMMU_BASE;
965
966 /* Read SMMU_ROOT_IDR0.BA_REALM[31:22] register field */
967 o_realm = mmio_read_32(FVP_RMM_SMMU_BASE + SMMU_ROOT_IDR0) &
968 SMMU_ROOT_IDR0_BA_REALM_MASK;
969 /*
970 * Calculate the base address offset of Realm Register Page 0.
971 * O_REALM = 0x20000 + (BA_REALM * 0x10000)
972 * SMMU_REALM_BASE = SMMU_PAGE_0_BASE + O_REALM
973 */
974 o_realm = 0x20000 + (o_realm >> (SMMU_ROOT_IDR0_BA_REALM_SHIFT - 16U));
975
976 smmu_ptr[0].smmu_r_base = FVP_RMM_SMMU_BASE + o_realm;
977
978 /* Update checksum */
979 checksum += checksum_calc((uint64_t *)smmu_ptr,
980 sizeof(struct smmu_info) * num_smmus);
981 /* Checksum must be 0 */
982 manifest->plat_smmu.checksum = ~checksum + 1UL;
983
984 /* Calculate the checksum of the plat_root_complex structure */
985 checksum = num_root_complex + (uint64_t)root_complex_ptr;
986
987 /* Zero out PCIe root complex info structures */
988 (void)memset((void *)root_complex_ptr, 0,
989 sizeof(struct root_complex_info) * num_root_complex);
990
991 /* Set pointers for data in manifest */
992 rc_ptr = root_complex_ptr;
993 rp_ptr = root_port_ptr;
994 bdf_ptr = bdf_mapping_ptr;
995
996 /* Fill PCIe root complex info structures */
997 for (unsigned long i = 0U; i < num_root_complex; i++) {
998 const struct root_complex_info *rc_info = &rc_data[i];
999 const struct root_port_info *rp_info = rc_info->root_ports;
1000
1001 /* Copy root complex data, except root_ports pointer */
1002 (void)memcpy((void *)rc_ptr, (void *)rc_info,
1003 sizeof(struct root_complex_info) - sizeof(struct root_port_info *));
1004
1005 /* Set root_ports for root complex */
1006 rc_ptr->root_ports = rp_ptr;
1007
1008 /* Scan root ports */
1009 for (unsigned int j = 0U; j < rc_ptr->num_root_ports; j++) {
1010 const struct bdf_mapping_info *bdf_info = rp_info->bdf_mappings;
1011
1012 /* Copy root port data, except bdf_mappings pointer */
1013 (void)memcpy((void *)rp_ptr, (void *)rp_info,
1014 sizeof(struct root_port_info) - sizeof(struct bdf_mapping_info *));
1015
1016 /* Set bdf_mappings for root port */
1017 rp_ptr->bdf_mappings = bdf_ptr;
1018
1019 /* Copy all BDF mappings for root port */
1020 (void)memcpy((void *)bdf_ptr, (void *)bdf_info,
1021 sizeof(struct bdf_mapping_info) * rp_ptr->num_bdf_mappings);
1022
1023 bdf_ptr += rp_ptr->num_bdf_mappings;
1024 rp_ptr++;
1025 rp_info++;
1026 }
1027 rc_ptr++;
1028 }
1029
1030 /* Check that all data are written in manifest */
1031 assert(rc_ptr == (root_complex_ptr + num_root_complex));
1032 assert(rp_ptr == (root_port_ptr + num_root_ports));
1033 assert(bdf_ptr == (bdf_mapping_ptr + num_bdf_mappings));
1034
1035 /* Update checksum for all PCIe data */
1036 checksum += checksum_calc((uint64_t *)root_complex_ptr,
1037 (uintptr_t)bdf_ptr - (uintptr_t)root_complex_ptr);
1038
1039 /* Checksum must be 0 */
1040 manifest->plat_root_complex.checksum = ~checksum + 1UL;
1041
1042 return 0;
1043 }
1044
1045 /*
1046 * Update encryption key associated with @mecid.
1047 */
plat_rmmd_mecid_key_update(uint16_t mecid,unsigned int reason)1048 int plat_rmmd_mecid_key_update(uint16_t mecid, unsigned int reason)
1049 {
1050 /*
1051 * FVP does not provide an interface to change the encryption key associated
1052 * with MECID. Hence always return success.
1053 */
1054 return 0;
1055 }
1056 #endif /* ENABLE_RMM */
1057