1 /* 2 * Copyright (c) 2013-2026, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /* Extracts the CPU part number from MIDR for checking CPU match */ 28 #define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 29 30 /******************************************************************************* 31 * MPIDR macros 32 ******************************************************************************/ 33 #define MPIDR_MT_MASK (ULL(1) << 24) 34 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 35 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 36 #define MPIDR_AFFINITY_BITS U(8) 37 #define MPIDR_AFFLVL_MASK ULL(0xff) 38 #define MPIDR_AFF0_SHIFT U(0) 39 #define MPIDR_AFF1_SHIFT U(8) 40 #define MPIDR_AFF2_SHIFT U(16) 41 #define MPIDR_AFF3_SHIFT U(32) 42 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 43 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 44 #define MPIDR_AFFLVL_SHIFT U(3) 45 #define MPIDR_AFFLVL0 ULL(0x0) 46 #define MPIDR_AFFLVL1 ULL(0x1) 47 #define MPIDR_AFFLVL2 ULL(0x2) 48 #define MPIDR_AFFLVL3 ULL(0x3) 49 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 50 #define MPIDR_AFFLVL0_VAL(mpidr) \ 51 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 52 #define MPIDR_AFFLVL1_VAL(mpidr) \ 53 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 54 #define MPIDR_AFFLVL2_VAL(mpidr) \ 55 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 56 #define MPIDR_AFFLVL3_VAL(mpidr) \ 57 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 58 /* 59 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 60 * add one while using this macro to define array sizes. 61 * TODO: Support only the first 3 affinity levels for now. 62 */ 63 #define MPIDR_MAX_AFFLVL U(2) 64 65 #define MPID_MASK (MPIDR_MT_MASK | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 67 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 68 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 69 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 70 71 #define MPIDR_AFF_ID(mpid, n) \ 72 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 73 74 /* 75 * An invalid MPID. This value can be used by functions that return an MPID to 76 * indicate an error. 77 */ 78 #define INVALID_MPID U(0xFFFFFFFF) 79 80 /******************************************************************************* 81 * Definitions for Exception vector offsets 82 ******************************************************************************/ 83 #define CURRENT_EL_SP0 0x0 84 #define CURRENT_EL_SPX 0x200 85 #define LOWER_EL_AARCH64 0x400 86 #define LOWER_EL_AARCH32 0x600 87 88 #define SYNC_EXCEPTION 0x0 89 #define IRQ_EXCEPTION 0x80 90 #define FIQ_EXCEPTION 0x100 91 #define SERROR_EXCEPTION 0x180 92 93 /******************************************************************************* 94 * Encodings for GICv5 EL3 system registers 95 ******************************************************************************/ 96 #define ICC_PPI_DOMAINR0_EL3 S3_6_C12_C8_4 97 #define ICC_PPI_DOMAINR1_EL3 S3_6_C12_C8_5 98 #define ICC_PPI_DOMAINR2_EL3 S3_6_C12_C8_6 99 #define ICC_PPI_DOMAINR3_EL3 S3_6_C12_C8_7 100 101 #define ICC_PPI_DOMAINR_FIELD_MASK ULL(0x3) 102 #define ICC_PPI_DOMAINR_COUNT (32) 103 104 /******************************************************************************* 105 * Definitions for CPU system register interface to GICv3 106 ******************************************************************************/ 107 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 108 #define ICC_SGI1R S3_0_C12_C11_5 109 #define ICC_ASGI1R S3_0_C12_C11_6 110 #define ICC_SRE_EL1 S3_0_C12_C12_5 111 #define ICC_SRE_EL2 S3_4_C12_C9_5 112 #define ICC_SRE_EL3 S3_6_C12_C12_5 113 #define ICC_CTLR_EL1 S3_0_C12_C12_4 114 #define ICC_CTLR_EL3 S3_6_C12_C12_4 115 #define ICC_PMR_EL1 S3_0_C4_C6_0 116 #define ICC_RPR_EL1 S3_0_C12_C11_3 117 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 118 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 119 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 120 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 121 #define ICC_IAR0_EL1 S3_0_c12_c8_0 122 #define ICC_IAR1_EL1 S3_0_c12_c12_0 123 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 124 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 125 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 126 127 /******************************************************************************* 128 * Definitions for EL2 system registers for save/restore routine 129 ******************************************************************************/ 130 #define CNTPOFF_EL2 S3_4_C14_C0_6 131 #define HDFGRTR2_EL2 S3_4_C3_C1_0 132 #define HDFGWTR2_EL2 S3_4_C3_C1_1 133 #define HFGRTR2_EL2 S3_4_C3_C1_2 134 #define HFGWTR2_EL2 S3_4_C3_C1_3 135 #define HDFGRTR_EL2 S3_4_C3_C1_4 136 #define HDFGWTR_EL2 S3_4_C3_C1_5 137 #define HAFGRTR_EL2 S3_4_C3_C1_6 138 #define HFGITR2_EL2 S3_4_C3_C1_7 139 #define HFGITR_EL2 S3_4_C1_C1_6 140 #define HFGRTR_EL2 S3_4_C1_C1_4 141 #define HFGWTR_EL2 S3_4_C1_C1_5 142 #define ICH_HCR_EL2 S3_4_C12_C11_0 143 #define ICH_VMCR_EL2 S3_4_C12_C11_7 144 #define MPAMVPM0_EL2 S3_4_C10_C6_0 145 #define MPAMVPM1_EL2 S3_4_C10_C6_1 146 #define MPAMVPM2_EL2 S3_4_C10_C6_2 147 #define MPAMVPM3_EL2 S3_4_C10_C6_3 148 #define MPAMVPM4_EL2 S3_4_C10_C6_4 149 #define MPAMVPM5_EL2 S3_4_C10_C6_5 150 #define MPAMVPM6_EL2 S3_4_C10_C6_6 151 #define MPAMVPM7_EL2 S3_4_C10_C6_7 152 #define MPAMVPMV_EL2 S3_4_C10_C4_1 153 #define VNCR_EL2 S3_4_C2_C2_0 154 #define PMSCR_EL2 S3_4_C9_C9_0 155 #define TFSR_EL2 S3_4_C5_C6_0 156 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 157 #define TTBR1_EL2 S3_4_C2_C0_1 158 159 #define HAFGRTR_EL2_INIT_VAL ULL(0) 160 161 /******************************************************************************* 162 * Generic timer memory mapped registers & offsets 163 ******************************************************************************/ 164 #define CNTCR_OFF U(0x000) 165 #define CNTCV_OFF U(0x008) 166 #define CNTFID_OFF U(0x020) 167 168 #define CNTCR_EN (U(1) << 0) 169 #define CNTCR_HDBG (U(1) << 1) 170 #define CNTCR_FCREQ(x) ((x) << 8) 171 172 /******************************************************************************* 173 * System register bit definitions 174 ******************************************************************************/ 175 /* CLIDR definitions */ 176 #define LOUIS_SHIFT U(21) 177 #define LOC_SHIFT U(24) 178 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 179 #define CLIDR_FIELD_WIDTH U(3) 180 181 /* CSSELR definitions */ 182 #define LEVEL_SHIFT U(1) 183 184 /* Data cache set/way op type defines */ 185 #define DCISW U(0x0) 186 #define DCCISW U(0x1) 187 #if ERRATA_A53_827319 188 #define DCCSW DCCISW 189 #else 190 #define DCCSW U(0x2) 191 #endif 192 193 #define ID_REG_FIELD_MASK ULL(0xf) 194 195 /******************************************************************************* 196 * PFR0_EL1 - Definitions for AArch32 Processor Feature Register 0 197 ******************************************************************************/ 198 #define ID_PFR0_EL1 S3_0_C0_C1_0 199 200 /******************************************************************************* 201 * PFR2_EL1 - Definitions for AArch32 Processor Feature Register 2 202 ******************************************************************************/ 203 #define ID_PFR2_EL1 S3_0_C0_C3_4 204 205 /******************************************************************************* 206 * ID_ISAR6_EL1 - Definition for AArch32 Instruction Set Attribute Register 6 207 ******************************************************************************/ 208 #define ID_ISAR6_EL1 S3_0_C0_C2_7 209 210 /******************************************************************************* 211 * ID_DFR1_EL1 - Definition for AArch32 Debug Feature Register 1 212 ******************************************************************************/ 213 #define ID_DFR1_EL1 S3_0_C0_C3_5 214 215 /* ID_AA64PFR0_EL1 definitions */ 216 #define ID_AA64PFR0_EL0_SHIFT U(0) 217 #define ID_AA64PFR0_EL1_SHIFT U(4) 218 #define ID_AA64PFR0_EL2_SHIFT U(8) 219 #define ID_AA64PFR0_EL3_SHIFT U(12) 220 221 #define ID_AA64PFR0_AMU_SHIFT U(44) 222 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 223 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 224 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 225 226 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 227 #define ID_AA64PFR0_EL0_MASK ID_AA64PFR0_ELX_MASK 228 #define ID_AA64PFR0_EL1_MASK ID_AA64PFR0_ELX_MASK 229 #define ID_AA64PFR0_EL2_MASK ID_AA64PFR0_ELX_MASK 230 #define ID_AA64PFR0_EL3_MASK ID_AA64PFR0_ELX_MASK 231 232 #define ID_AA64PFR0_GIC_SHIFT U(24) 233 #define ID_AA64PFR0_GIC_WIDTH U(4) 234 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 235 236 #define ID_AA64PFR0_SVE_SHIFT U(32) 237 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 238 #define ID_AA64PFR0_SVE_LENGTH U(4) 239 #define SVE_IMPLEMENTED ULL(0x1) 240 241 #define ID_AA64PFR0_SEL2_SHIFT U(36) 242 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 243 244 #define ID_AA64PFR0_MPAM_SHIFT U(40) 245 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 246 247 #define ID_AA64PFR0_DIT_SHIFT U(48) 248 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 249 #define ID_AA64PFR0_DIT_LENGTH U(4) 250 #define DIT_IMPLEMENTED ULL(1) 251 252 #define ID_AA64PFR0_CSV2_SHIFT U(56) 253 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 254 #define ID_AA64PFR0_CSV2_LENGTH U(4) 255 #define CSV2_2_IMPLEMENTED ULL(0x2) 256 #define CSV2_3_IMPLEMENTED ULL(0x3) 257 258 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 259 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 260 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 261 #define RME_NOT_IMPLEMENTED ULL(0) 262 #define RME_GPC2_IMPLEMENTED ULL(0x2) 263 264 #define ID_AA64PFR0_RAS_SHIFT U(28) 265 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 266 #define ID_AA64PFR0_RAS_LENGTH U(4) 267 268 /* Exception level handling */ 269 #define EL_IMPL_NONE ULL(0) 270 #define EL_IMPL_A64ONLY ULL(1) 271 #define EL_IMPL_A64_A32 ULL(2) 272 273 /* ID_AA64DFR0_EL1.DebugVer definitions */ 274 #define ID_AA64DFR0_DEBUGVER_SHIFT U(0) 275 #define ID_AA64DFR0_DEBUGVER_MASK ULL(0xf) 276 #define DEBUGVER_V8P9_IMPLEMENTED ULL(0xb) 277 278 /* ID_AA64DFR0_EL1.TraceVer definitions */ 279 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 280 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 281 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 282 283 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 284 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 285 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 286 #define TRACEFILT_IMPLEMENTED ULL(1) 287 288 #define ID_AA64DFR0_PMUVER_LENGTH U(4) 289 #define ID_AA64DFR0_PMUVER_SHIFT U(8) 290 #define ID_AA64DFR0_PMUVER_MASK U(0xf) 291 #define ID_AA64DFR0_PMUVER_PMUV3 U(1) 292 #define ID_AA64DFR0_PMUVER_PMUV3P9 U(9) 293 #define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) 294 295 /* ID_AA64DFR0_EL1.SEBEP definitions */ 296 #define ID_AA64DFR0_SEBEP_SHIFT U(24) 297 #define ID_AA64DFR0_SEBEP_MASK ULL(0xf) 298 #define SEBEP_IMPLEMENTED ULL(1) 299 300 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 301 #define ID_AA64DFR0_PMS_SHIFT U(32) 302 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 303 #define SPE_IMPLEMENTED ULL(0x1) 304 #define SPE_NOT_IMPLEMENTED ULL(0x0) 305 306 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 307 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 308 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 309 #define TRACEBUFFER_IMPLEMENTED ULL(1) 310 311 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 312 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 313 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 314 #define MTPMU_IMPLEMENTED ULL(1) 315 #define MTPMU_NOT_IMPLEMENTED ULL(15) 316 317 /* ID_AA64DFR0_EL1.BRBE definitions */ 318 #define ID_AA64DFR0_BRBE_SHIFT U(52) 319 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 320 #define BRBE_IMPLEMENTED ULL(1) 321 322 /* ID_AA64DFR1_EL1 definitions */ 323 #define ID_AA64DFR1_EBEP_SHIFT U(48) 324 #define ID_AA64DFR1_EBEP_MASK ULL(0xf) 325 #define EBEP_IMPLEMENTED ULL(1) 326 327 #define ID_AA64DFR1_BRP_SHIFT U(8) 328 #define ID_AA64DFR1_BRP_WIDTH U(8) 329 330 /* ID_AA64DFR2_EL1 definitions */ 331 #define ID_AA64DFR2_STEP_SHIFT U(0) 332 #define ID_AA64DFR2_STEP_MASK ULL(0xf) 333 334 #define ID_AA64ZFR0_EL1 S3_0_C0_C4_4 335 #define ID_AA64FPFR0_EL1 S3_0_C0_C4_7 336 #define ID_AA64DFR2_EL1 S3_0_C0_C5_2 337 #define GMID_EL1 S3_1_C0_C0_4 338 339 /* ID_AA64ISAR0_EL1 definitions */ 340 #define ID_AA64ISAR0_ATOMIC_SHIFT U(20) 341 #define ID_AA64ISAR0_ATOMIC_MASK ULL(0xf) 342 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 343 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 344 345 #define ID_AA64ISAR0_AES_SHIFT U(0x4) 346 #define ID_AA64ISAR0_AES_MASK ULL(0xf) 347 #define ID_AA64ISAR0_SHA1_SHIFT U(0x8) 348 #define ID_AA64ISAR0_SHA1_MASK ULL(0xf) 349 #define ID_AA64ISAR0_SHA2_SHIFT U(0xc) 350 #define ID_AA64ISAR0_SHA2_MASK ULL(0xf) 351 352 /* ID_AA64ISAR1_EL1 definitions */ 353 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 354 355 #define ID_AA64ISAR1_LS64_SHIFT U(60) 356 #define ID_AA64ISAR1_LS64_MASK ULL(0xf) 357 #define LS64_ACCDATA_IMPLEMENTED ULL(0x3) 358 #define LS64_V_IMPLEMENTED ULL(0x2) 359 #define LS64_IMPLEMENTED ULL(0x1) 360 #define LS64_NOT_IMPLEMENTED ULL(0x0) 361 362 #define ID_AA64ISAR1_SB_SHIFT U(36) 363 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 364 #define SB_IMPLEMENTED ULL(0x1) 365 #define SB_NOT_IMPLEMENTED ULL(0x0) 366 367 #define ID_AA64ISAR1_GPI_SHIFT U(28) 368 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 369 #define ID_AA64ISAR1_GPA_SHIFT U(24) 370 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 371 372 #define ID_AA64ISAR1_API_SHIFT U(8) 373 #define ID_AA64ISAR1_API_MASK ULL(0xf) 374 #define ID_AA64ISAR1_APA_SHIFT U(4) 375 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 376 377 /* ID_AA64ISAR2_EL1 definitions */ 378 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 379 #define ID_AA64ISAR2_EL1_MOPS_SHIFT U(16) 380 #define ID_AA64ISAR2_EL1_MOPS_MASK ULL(0xf) 381 382 #define MOPS_IMPLEMENTED ULL(0x1) 383 384 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 385 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 386 387 #define ID_AA64ISAR2_APA3_SHIFT U(12) 388 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 389 390 #define ID_AA64ISAR2_CLRBHB_SHIFT U(28) 391 #define ID_AA64ISAR2_CLRBHB_MASK ULL(0xf) 392 393 #define ID_AA64ISAR2_SYSREG128_SHIFT U(32) 394 #define ID_AA64ISAR2_SYSREG128_MASK ULL(0xf) 395 396 /* ID_AA64ISAR3_EL1 definitions */ 397 #define ID_AA64ISAR3_EL1 S3_0_C0_C6_3 398 #define ID_AA64ISAR3_EL1_CPA_SHIFT U(0) 399 #define ID_AA64ISAR3_EL1_CPA_MASK ULL(0xf) 400 401 #define CPA2_IMPLEMENTED ULL(0x2) 402 403 /* ID_AA64MMFR0_EL1 definitions */ 404 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 405 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 406 407 #define PARANGE_0000 U(32) 408 #define PARANGE_0001 U(36) 409 #define PARANGE_0010 U(40) 410 #define PARANGE_0011 U(42) 411 #define PARANGE_0100 U(44) 412 #define PARANGE_0101 U(48) 413 #define PARANGE_0110 U(52) 414 #define PARANGE_0111 U(56) 415 416 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 417 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 418 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 419 #define ECV_IMPLEMENTED ULL(0x1) 420 421 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 422 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 423 #define FGT2_IMPLEMENTED ULL(0x2) 424 #define FGT_IMPLEMENTED ULL(0x1) 425 #define FGT_NOT_IMPLEMENTED ULL(0x0) 426 427 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 428 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 429 430 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 431 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 432 433 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 434 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 435 #define TGRAN16_IMPLEMENTED ULL(0x1) 436 437 /* ID_AA64MMFR1_EL1 definitions */ 438 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 439 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 440 #define TWED_IMPLEMENTED ULL(0x1) 441 442 #define ID_AA64MMFR1_EL1_HAFDBS_SHIFT U(0) 443 #define ID_AA64MMFR1_EL1_HAFDBS_MASK ULL(0xf) 444 #define HDBSS_IMPLEMENTED ULL(0x4) 445 446 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 447 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 448 #define PAN_IMPLEMENTED ULL(0x1) 449 #define PAN2_IMPLEMENTED ULL(0x2) 450 #define PAN3_IMPLEMENTED ULL(0x3) 451 452 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 453 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 454 455 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 456 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 457 #define HCX_IMPLEMENTED ULL(0x1) 458 459 /* ID_AA64MMFR2_EL1 definitions */ 460 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 461 462 #define ID_AA64MMFR2_EL1_IDS_SHIFT U(36) 463 #define ID_AA64MMFR2_EL1_IDS_MASK ULL(0xf) 464 465 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 466 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 467 468 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 469 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 470 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 471 472 #define ID_AA64MMFR2_EL1_UAO_SHIFT U(4) 473 #define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf) 474 475 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 476 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 477 478 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 479 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 480 #define NV2_IMPLEMENTED ULL(0x2) 481 482 /* ID_AA64MMFR3_EL1 definitions */ 483 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 484 485 #define ID_AA64MMFR3_EL1_D128_SHIFT U(32) 486 #define ID_AA64MMFR3_EL1_D128_MASK ULL(0xf) 487 #define D128_IMPLEMENTED ULL(0x1) 488 489 #define ID_AA64MMFR3_EL1_MEC_SHIFT U(28) 490 #define ID_AA64MMFR3_EL1_MEC_MASK ULL(0xf) 491 492 #define ID_AA64MMFR3_EL1_AIE_SHIFT U(24) 493 #define ID_AA64MMFR3_EL1_AIE_MASK ULL(0xf) 494 495 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 496 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 497 498 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 499 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 500 501 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 502 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 503 504 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 505 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 506 507 #define ID_AA64MMFR3_EL1_SCTLR2_SHIFT U(4) 508 #define ID_AA64MMFR3_EL1_SCTLR2_MASK ULL(0xf) 509 #define SCTLR2_IMPLEMENTED ULL(1) 510 511 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 512 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 513 514 /* ID_AA64MMFR4_EL1 definitions */ 515 #define ID_AA64MMFR4_EL1 S3_0_C0_C7_4 516 517 #define ID_AA64MMFR4_EL1_HACDBS_SHIFT U(12) 518 #define ID_AA64MMFR4_EL1_HACDBS_MASK ULL(0xf) 519 #define HACDBS_IMPLEMENTED ULL(0x1) 520 521 #define ID_AA64MMFR4_EL1_FGWTE3_SHIFT U(16) 522 #define ID_AA64MMFR4_EL1_FGWTE3_MASK ULL(0xf) 523 #define FGWTE3_IMPLEMENTED ULL(0x1) 524 525 #define ID_AA64MMFR4_EL1_RME_GDI_SHIFT U(28) 526 #define ID_AA64MMFR4_EL1_RME_GDI_MASK ULL(0xf) 527 #define ID_AA64MMFR4_EL1_RME_GDI_LENGTH U(4) 528 #define RME_GDI_IMPLEMENTED ULL(0x1) 529 530 /* ID_AA64PFR1_EL1 definitions */ 531 532 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 533 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 534 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 535 536 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 537 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 538 #define SSBS_NOT_IMPLEMENTED ULL(0) /* No architectural SSBS support */ 539 540 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 541 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 542 543 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 544 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 545 #define RNG_TRAP_IMPLEMENTED ULL(0x1) 546 547 #define ID_AA64PFR1_EL1_NMI_SHIFT U(36) 548 #define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf) 549 #define NMI_IMPLEMENTED ULL(1) 550 551 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 552 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 553 #define GCS_IMPLEMENTED ULL(1) 554 555 #define ID_AA64PFR1_EL1_THE_SHIFT U(48) 556 #define ID_AA64PFR1_EL1_THE_MASK ULL(0xf) 557 #define THE_IMPLEMENTED ULL(1) 558 559 #define ID_AA64PFR1_EL1_PFAR_SHIFT U(60) 560 #define ID_AA64PFR1_EL1_PFAR_MASK ULL(0xf) 561 562 /* ID_AA64PFR1_EL1.CE field: Morello architecture presence (bits [23:20]) */ 563 #define ID_AA64PFR1_EL1_CE_SHIFT U(20) 564 #define ID_AA64PFR1_EL1_CE_MASK ULL(0xf) 565 /* 0b0000 means Morello arch is not present, 0b0001 means it is present */ 566 #define MORELLO_EXTENSION_IMPLEMENTED ULL(0x1) 567 #define CSCR_EL3_SETTAG ULL(0x1) 568 569 /* ID_AA64PFR2_EL1 definitions */ 570 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 571 572 #define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) 573 #define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf) 574 575 #define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4) 576 #define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf) 577 578 #define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8) 579 #define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf) 580 581 #define ID_AA64PFR2_EL1_UINJ_SHIFT U(16) 582 #define ID_AA64PFR2_EL1_UINJ_MASK ULL(0xf) 583 #define UINJ_IMPLEMENTED ULL(0x1) 584 585 #define ID_AA64PFR2_EL1_FPMR_SHIFT U(32) 586 #define ID_AA64PFR2_EL1_FPMR_MASK ULL(0xf) 587 588 #define FPMR_IMPLEMENTED ULL(0x1) 589 590 #define VDISR_EL2 S3_4_C12_C1_1 591 #define VSESR_EL2 S3_4_C5_C2_3 592 593 /* Memory Tagging Extension is not implemented */ 594 #define MTE_UNIMPLEMENTED U(0) 595 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 596 #define MTE_IMPLEMENTED_EL0 U(1) 597 /* FEAT_MTE2: Full MTE is implemented */ 598 #define MTE_IMPLEMENTED_ELX U(2) 599 /* 600 * FEAT_MTE3: MTE is implemented with support for 601 * asymmetric Tag Check Fault handling 602 */ 603 #define MTE_IMPLEMENTED_ASY U(3) 604 605 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 606 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 607 608 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 609 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 610 #define ID_AA64PFR1_EL1_SME_WIDTH U(4) 611 #define SME_IMPLEMENTED ULL(0x1) 612 #define SME2_IMPLEMENTED ULL(0x2) 613 #define SME_NOT_IMPLEMENTED ULL(0x0) 614 615 /* ID_AA64PFR2_EL1 definitions */ 616 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 617 #define ID_AA64PFR2_EL1_GCIE_SHIFT 12 618 #define ID_AA64PFR2_EL1_GCIE_MASK ULL(0xf) 619 620 /* ID_PFR1_EL1 definitions */ 621 #define ID_PFR1_VIRTEXT_SHIFT U(12) 622 #define ID_PFR1_VIRTEXT_MASK U(0xf) 623 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 624 & ID_PFR1_VIRTEXT_MASK) 625 626 /* SCTLR definitions */ 627 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 628 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 629 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 630 631 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 632 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 633 634 #define SCTLR_AARCH32_EL1_RES1 \ 635 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 636 (U(1) << 4) | (U(1) << 3)) 637 638 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 639 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 640 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 641 642 #define SCTLR_M_BIT (ULL(1) << 0) 643 #define SCTLR_A_BIT (ULL(1) << 1) 644 #define SCTLR_C_BIT (ULL(1) << 2) 645 #define SCTLR_SA_BIT (ULL(1) << 3) 646 #define SCTLR_SA0_BIT (ULL(1) << 4) 647 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 648 #define SCTLR_nAA_BIT (ULL(1) << 6) 649 #define SCTLR_ITD_BIT (ULL(1) << 7) 650 #define SCTLR_SED_BIT (ULL(1) << 8) 651 #define SCTLR_UMA_BIT (ULL(1) << 9) 652 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 653 #define SCTLR_EOS_BIT (ULL(1) << 11) 654 #define SCTLR_I_BIT (ULL(1) << 12) 655 #define SCTLR_EnDB_BIT (ULL(1) << 13) 656 #define SCTLR_DZE_BIT (ULL(1) << 14) 657 #define SCTLR_UCT_BIT (ULL(1) << 15) 658 #define SCTLR_NTWI_BIT (ULL(1) << 16) 659 #define SCTLR_NTWE_BIT (ULL(1) << 18) 660 #define SCTLR_WXN_BIT (ULL(1) << 19) 661 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 662 #define SCTLR_IESB_BIT (ULL(1) << 21) 663 #define SCTLR_EIS_BIT (ULL(1) << 22) 664 #define SCTLR_SPAN_BIT (ULL(1) << 23) 665 #define SCTLR_E0E_BIT (ULL(1) << 24) 666 #define SCTLR_EE_BIT (ULL(1) << 25) 667 #define SCTLR_UCI_BIT (ULL(1) << 26) 668 #define SCTLR_EnDA_BIT (ULL(1) << 27) 669 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 670 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 671 #define SCTLR_EnIB_BIT (ULL(1) << 30) 672 #define SCTLR_EnIA_BIT (ULL(1) << 31) 673 #define SCTLR_BT0_BIT (ULL(1) << 35) 674 #define SCTLR_BT1_BIT (ULL(1) << 36) 675 #define SCTLR_BT_BIT (ULL(1) << 36) 676 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 677 #define SCTLR_TCF0_SHIFT U(38) 678 #define SCTLR_TCF0_MASK ULL(3) 679 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 680 #define SCTLR_SPINTMASK_BIT (ULL(1) << 62) 681 682 /* Tag Check Faults in EL0 have no effect on the PE */ 683 #define SCTLR_TCF0_NO_EFFECT U(0) 684 /* Tag Check Faults in EL0 cause a synchronous exception */ 685 #define SCTLR_TCF0_SYNC U(1) 686 /* Tag Check Faults in EL0 are asynchronously accumulated */ 687 #define SCTLR_TCF0_ASYNC U(2) 688 /* 689 * Tag Check Faults in EL0 cause a synchronous exception on reads, 690 * and are asynchronously accumulated on writes 691 */ 692 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 693 694 #define SCTLR_TCF_SHIFT U(40) 695 #define SCTLR_TCF_MASK ULL(3) 696 697 /* Tag Check Faults in EL1 have no effect on the PE */ 698 #define SCTLR_TCF_NO_EFFECT U(0) 699 /* Tag Check Faults in EL1 cause a synchronous exception */ 700 #define SCTLR_TCF_SYNC U(1) 701 /* Tag Check Faults in EL1 are asynchronously accumulated */ 702 #define SCTLR_TCF_ASYNC U(2) 703 /* 704 * Tag Check Faults in EL1 cause a synchronous exception on reads, 705 * and are asynchronously accumulated on writes 706 */ 707 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 708 709 #define SCTLR_ATA0_BIT (ULL(1) << 42) 710 #define SCTLR_ATA_BIT (ULL(1) << 43) 711 #define SCTLR_DSSBS_SHIFT U(44) 712 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 713 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 714 #define SCTLR_TWEDEL_SHIFT U(46) 715 #define SCTLR_TWEDEL_MASK ULL(0xf) 716 #define SCTLR_EnASR_BIT (ULL(1) << 54) 717 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 718 #define SCTLR_EnALS_BIT (ULL(1) << 56) 719 #define SCTLR_EPAN_BIT (ULL(1) << 57) 720 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 721 722 #define SCTLR2_EnPACM_BIT (ULL(1) << 7) 723 #define SCTLR2_CPTA_BIT (ULL(1) << 9) 724 #define SCTLR2_CPTM_BIT (ULL(1) << 11) 725 726 /* SCTLR2 currently has no RES1 fields so reset to 0 */ 727 #define SCTLR2_RESET_VAL ULL(0) 728 729 /* CPACR_EL1 definitions */ 730 #define CPACR_EL1_FPEN(x) ((x) << 20) 731 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 732 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 733 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 734 #define CPACR_EL1_SMEN_SHIFT U(24) 735 #define CPACR_EL1_SMEN_MASK ULL(0x3) 736 737 /* SCR definitions */ 738 #if ENABLE_FEAT_GCIE 739 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5) | SCR_FIQ_BIT) 740 #else 741 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 742 #endif 743 #define SCR_NSE_SHIFT U(62) 744 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 745 #define SCR_HACDBSEn_BIT (UL(1) << 61) 746 #define SCR_HDBSSEn_BIT (UL(1) << 60) 747 #define SCR_FGTEN2_BIT (UL(1) << 59) 748 #define SCR_PFAREn_BIT (UL(1) << 53) 749 #define SCR_EnFPM_BIT (ULL(1) << 50) 750 #define SCR_MECEn_BIT (UL(1) << 49) 751 #define SCR_GPF_BIT (UL(1) << 48) 752 #define SCR_D128En_BIT (UL(1) << 47) 753 #define SCR_AIEn_BIT (UL(1) << 46) 754 #define SCR_TWEDEL_SHIFT U(30) 755 #define SCR_TWEDEL_MASK ULL(0xf) 756 #define SCR_PIEN_BIT (UL(1) << 45) 757 #define SCR_SCTLR2En_BIT (UL(1) << 44) 758 #define SCR_TCR2EN_BIT (UL(1) << 43) 759 #define SCR_RCWMASKEn_BIT (UL(1) << 42) 760 #define SCR_ENTP2_SHIFT U(41) 761 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 762 #define SCR_TRNDR_BIT (UL(1) << 40) 763 #define SCR_GCSEn_BIT (UL(1) << 39) 764 #define SCR_HXEn_BIT (UL(1) << 38) 765 #define SCR_ADEn_BIT (UL(1) << 37) 766 #define SCR_EnAS0_BIT (UL(1) << 36) 767 #define SCR_AMVOFFEN_SHIFT U(35) 768 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 769 #define SCR_TWEDEn_BIT (UL(1) << 29) 770 #define SCR_ECVEN_BIT (UL(1) << 28) 771 #define SCR_FGTEN_BIT (UL(1) << 27) 772 #define SCR_ATA_BIT (UL(1) << 26) 773 #define SCR_EnSCXT_BIT (UL(1) << 25) 774 #define SCR_TID5_BIT (UL(1) << 23) 775 #define SCR_TID3_BIT (UL(1) << 22) 776 #define SCR_FIEN_BIT (UL(1) << 21) 777 #define SCR_EEL2_SHIFT U(18) 778 #define SCR_EEL2_BIT (UL(1) << SCR_EEL2_SHIFT) 779 #define SCR_API_BIT (UL(1) << 17) 780 #define SCR_APK_BIT (UL(1) << 16) 781 #define SCR_TERR_BIT (UL(1) << 15) 782 #define SCR_TWE_BIT (UL(1) << 13) 783 #define SCR_TWI_BIT (UL(1) << 12) 784 #define SCR_ST_BIT (UL(1) << 11) 785 #define SCR_RW_BIT (UL(1) << 10) 786 #define SCR_SIF_BIT (UL(1) << 9) 787 #define SCR_HCE_BIT (UL(1) << 8) 788 #define SCR_SMD_BIT (UL(1) << 7) 789 #define SCR_EA_BIT (UL(1) << 3) 790 #define SCR_FIQ_BIT (UL(1) << 2) 791 #define SCR_IRQ_BIT (UL(1) << 1) 792 #define SCR_NS_BIT (UL(1) << 0) 793 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 794 #define SCR_RESET_VAL SCR_RES1_BITS 795 796 /* MDCR_EL3 definitions */ 797 #define MDCR_EnSTEPOP_BIT (ULL(1) << 50) 798 #define MDCR_EBWE_BIT (ULL(1) << 43) 799 #define MDCR_EnPMS3_BIT (ULL(1) << 42) 800 #define MDCR_PMEE(x) ((x) << 40) 801 #define MDCR_PMEE_CTRL_EL2 ULL(0x1) 802 #define MDCR_E3BREC_BIT (ULL(1) << 38) 803 #define MDCR_E3BREW_BIT (ULL(1) << 37) 804 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 805 #define MDCR_MPMX_BIT (ULL(1) << 35) 806 #define MDCR_MCCD_BIT (ULL(1) << 34) 807 #define MDCR_SBRBE_SHIFT U(32) 808 #define MDCR_SBRBE(x) ((x) << MDCR_SBRBE_SHIFT) 809 #define MDCR_SBRBE_ALL ULL(0x3) 810 #define MDCR_SBRBE_NS ULL(0x1) 811 #define MDCR_NSTB_EN_BIT (ULL(1) << 24) 812 #define MDCR_NSTB_SS_BIT (ULL(1) << 25) 813 #define MDCR_NSTBE_BIT (ULL(1) << 26) 814 #define MDCR_MTPME_BIT (ULL(1) << 28) 815 #define MDCR_TDCC_BIT (ULL(1) << 27) 816 #define MDCR_SCCD_BIT (ULL(1) << 23) 817 #define MDCR_EPMAD_BIT (ULL(1) << 21) 818 #define MDCR_EDAD_BIT (ULL(1) << 20) 819 #define MDCR_TTRF_BIT (ULL(1) << 19) 820 #define MDCR_STE_BIT (ULL(1) << 18) 821 #define MDCR_SPME_BIT (ULL(1) << 17) 822 #define MDCR_SDD_BIT (ULL(1) << 16) 823 #define MDCR_SPD32(x) ((x) << 14) 824 #define MDCR_SPD32_LEGACY ULL(0x0) 825 #define MDCR_SPD32_DISABLE ULL(0x2) 826 #define MDCR_SPD32_ENABLE ULL(0x3) 827 #define MDCR_NSPB_SS_BIT (ULL(1) << 13) 828 #define MDCR_NSPB_EN_BIT (ULL(1) << 12) 829 #define MDCR_NSPBE_BIT (ULL(1) << 11) 830 #define MDCR_TDOSA_BIT (ULL(1) << 10) 831 #define MDCR_TDA_BIT (ULL(1) << 9) 832 #define MDCR_EnPM2_BIT (ULL(1) << 7) 833 #define MDCR_TPM_BIT (ULL(1) << 6) 834 #define MDCR_RLTE_BIT (ULL(1) << 0) 835 #define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT 836 837 /* MDCR_EL2 definitions */ 838 #define MDCR_EL2_MTPME (ULL(1) << 28) 839 #define MDCR_EL2_HLP_BIT (ULL(1) << 26) 840 #define MDCR_EL2_E2TB(x) ULL((x) << 24) 841 #define MDCR_EL2_E2TB_EL1 ULL(0x3) 842 #define MDCR_EL2_HCCD_BIT (ULL(1) << 23) 843 #define MDCR_EL2_TTRF (ULL(1) << 19) 844 #define MDCR_EL2_HPMD_BIT (ULL(1) << 17) 845 #define MDCR_EL2_TPMS (ULL(1) << 14) 846 #define MDCR_EL2_E2PB(x) ULL((x) << 12) 847 #define MDCR_EL2_E2PB_EL1 ULL(0x3) 848 #define MDCR_EL2_TDRA_BIT (ULL(1) << 11) 849 #define MDCR_EL2_TDOSA_BIT (ULL(1) << 10) 850 #define MDCR_EL2_TDA_BIT (ULL(1) << 9) 851 #define MDCR_EL2_TDE_BIT (ULL(1) << 8) 852 #define MDCR_EL2_HPME_BIT (ULL(1) << 7) 853 #define MDCR_EL2_TPM_BIT (ULL(1) << 6) 854 #define MDCR_EL2_TPMCR_BIT (ULL(1) << 5) 855 #define MDCR_EL2_HPMN_MASK ULL(0x1f) 856 #define MDCR_EL2_RESET_VAL ULL(0x0) 857 858 /* HSTR_EL2 definitions */ 859 #define HSTR_EL2_RESET_VAL U(0x0) 860 #define HSTR_EL2_T_MASK U(0xff) 861 862 /* CNTHP_CTL_EL2 definitions */ 863 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 864 #define CNTHP_CTL_RESET_VAL U(0x0) 865 866 /* VTTBR_EL2 definitions */ 867 #define VTTBR_RESET_VAL ULL(0x0) 868 #define VTTBR_VMID_MASK ULL(0xff) 869 #define VTTBR_VMID_SHIFT U(48) 870 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 871 #define VTTBR_BADDR_SHIFT U(0) 872 873 /* HCR definitions */ 874 #define HCR_RESET_VAL ULL(0x0) 875 #define HCR_AMVOFFEN_SHIFT U(51) 876 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 877 #define HCR_TEA_BIT (ULL(1) << 47) 878 #define HCR_API_BIT (ULL(1) << 41) 879 #define HCR_APK_BIT (ULL(1) << 40) 880 #define HCR_E2H_BIT (ULL(1) << 34) 881 #define HCR_HCD_BIT (ULL(1) << 29) 882 #define HCR_TGE_BIT (ULL(1) << 27) 883 #define HCR_RW_SHIFT U(31) 884 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 885 #define HCR_TWE_BIT (ULL(1) << 14) 886 #define HCR_TWI_BIT (ULL(1) << 13) 887 #define HCR_AMO_BIT (ULL(1) << 5) 888 #define HCR_IMO_BIT (ULL(1) << 4) 889 #define HCR_FMO_BIT (ULL(1) << 3) 890 891 /* ISR definitions */ 892 #define ISR_A_SHIFT U(8) 893 #define ISR_I_SHIFT U(7) 894 #define ISR_F_SHIFT U(6) 895 896 /* CNTHCTL_EL2 definitions */ 897 #define CNTHCTL_RESET_VAL U(0x0) 898 #define EVNTEN_BIT (U(1) << 2) 899 #define EL1PCEN_BIT (U(1) << 1) 900 #define EL1PCTEN_BIT (U(1) << 0) 901 902 /* CNTKCTL_EL1 definitions */ 903 #define EL0PTEN_BIT (U(1) << 9) 904 #define EL0VTEN_BIT (U(1) << 8) 905 #define EL0PCTEN_BIT (U(1) << 0) 906 #define EL0VCTEN_BIT (U(1) << 1) 907 #define EVNTEN_BIT (U(1) << 2) 908 #define EVNTDIR_BIT (U(1) << 3) 909 #define EVNTI_SHIFT U(4) 910 #define EVNTI_MASK U(0xf) 911 912 /* CPTR_EL3 definitions */ 913 #define TCPAC_BIT (U(1) << 31) 914 #define TAM_SHIFT U(30) 915 #define TAM_BIT (U(1) << TAM_SHIFT) 916 #define TTA_BIT (U(1) << 20) 917 #define ESM_BIT (U(1) << 12) 918 #define TFP_BIT (U(1) << 10) 919 #define CPTR_EZ_BIT (U(1) << 8) 920 921 #if ENABLE_FEAT_MORELLO 922 #define EC_BIT (U(1) << 9) 923 /* 924 * Even though the morello spec doesnot have TAM_BIT defined it is included 925 * to keep the definition as close to other hardware as possible. Since bit 30 926 * is reserved in Morello it should not have any effect anyways. 927 */ 928 #define CPTR_EL3_RESET_VAL ((TAM_BIT | TTA_BIT | EC_BIT) & \ 929 ~(CPTR_EZ_BIT | ESM_BIT | TCPAC_BIT)) 930 #else 931 /* TCPAC is always set by default as the register is always present */ 932 #define CPTR_EL3_RESET_VAL ((TAM_BIT | TTA_BIT) & \ 933 ~(CPTR_EZ_BIT | ESM_BIT | TCPAC_BIT)) 934 #endif 935 936 /* CPTR_EL2 definitions */ 937 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 938 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 939 #define CPTR_EL2_TAM_SHIFT U(30) 940 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 941 #define CPTR_EL2_SMEN_MASK ULL(0x3) 942 #define CPTR_EL2_SMEN_SHIFT U(24) 943 #define CPTR_EL2_TTA_BIT (U(1) << 20) 944 #define CPTR_EL2_ZEN_MASK ULL(0x3) 945 #define CPTR_EL2_ZEN_SHIFT U(16) 946 #define CPTR_EL2_TSM_BIT (U(1) << 12) 947 #define CPTR_EL2_TFP_BIT (ULL(1) << 10) 948 #define CPTR_EL2_TZ_BIT (ULL(1) << 8) 949 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 950 951 /* VTCR_EL2 definitions */ 952 #define VTCR_RESET_VAL U(0x0) 953 #define VTCR_EL2_MSA (U(1) << 31) 954 955 /* CPSR/SPSR definitions */ 956 #define DAIF_FIQ_BIT (U(1) << 0) 957 #define DAIF_IRQ_BIT (U(1) << 1) 958 #define DAIF_ABT_BIT (U(1) << 2) 959 #define DAIF_DBG_BIT (U(1) << 3) 960 #define SPSR_V_BIT (U(1) << 28) 961 #define SPSR_C_BIT (U(1) << 29) 962 #define SPSR_Z_BIT (U(1) << 30) 963 #define SPSR_N_BIT (U(1) << 31) 964 #define SPSR_DAIF_SHIFT U(6) 965 #define SPSR_DAIF_MASK U(0xf) 966 967 #define SPSR_AIF_SHIFT U(6) 968 #define SPSR_AIF_MASK U(0x7) 969 970 #define SPSR_E_SHIFT U(9) 971 #define SPSR_E_MASK U(0x1) 972 #define SPSR_E_LITTLE U(0x0) 973 #define SPSR_E_BIG U(0x1) 974 975 #define SPSR_T_SHIFT U(5) 976 #define SPSR_T_MASK U(0x1) 977 #define SPSR_T_ARM U(0x0) 978 #define SPSR_T_THUMB U(0x1) 979 980 #define SPSR_M_SHIFT U(4) 981 #define SPSR_M_MASK U(0x1) 982 #define SPSR_M_WIDTH U(1) 983 #define SPSR_M_AARCH64 U(0x0) 984 #define SPSR_M_AARCH32 U(0x1) 985 #define SPSR_M_EL1H U(0x5) 986 #define SPSR_M_EL2H U(0x9) 987 988 #define SPSR_EL_SHIFT U(2) 989 #define SPSR_EL_WIDTH U(2) 990 991 #define SPSR_BTYPE_SHIFT_AARCH64 U(10) 992 #define SPSR_BTYPE_MASK_AARCH64 U(0x3) 993 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 994 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 995 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 996 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 997 #define SPSR_ALLINT_BIT_AARCH64 BIT_64(13) 998 #define SPSR_IL_BIT BIT_64(20) 999 #define SPSR_SS_BIT BIT_64(21) 1000 #define SPSR_PAN_BIT BIT_64(22) 1001 #define SPSR_UAO_BIT_AARCH64 BIT_64(23) 1002 #define SPSR_DIT_BIT BIT(24) 1003 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 1004 #define SPSR_PM_BIT_AARCH64 BIT_64(32) 1005 #define SPSR_PPEND_BIT BIT(33) 1006 #define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34) 1007 #define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT) 1008 #define SPSR_PACM_BIT_AARCH64 BIT_64(35) 1009 #define SPSR_UINJ_BIT BIT_64(36) 1010 1011 /* 1012 * SPSR_EL2 1013 * M=0x9 (0b1001 EL2h) 1014 * M[4]=0 1015 * DAIF=0xF Exceptions masked on entry. 1016 * BTYPE=0 BTI not yet supported. 1017 * SSBS=0 Not yet supported. 1018 * IL=0 Not an illegal exception return. 1019 * SS=0 Not single stepping. 1020 * PAN=1 RMM shouldn't access Unprivileged memory when running in VHE mode. 1021 * UAO=0 1022 * DIT=0 1023 * TCO=0 1024 * NZCV=0 1025 */ 1026 #define SPSR_EL2_REALM (SPSR_M_EL2H | (0xF << SPSR_DAIF_SHIFT) | \ 1027 SPSR_PAN_BIT) 1028 1029 #define DISABLE_ALL_EXCEPTIONS \ 1030 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 1031 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 1032 1033 /* 1034 * RMR_EL3 definitions 1035 */ 1036 #define RMR_EL3_RR_BIT (U(1) << 1) 1037 #define RMR_EL3_AA64_BIT (U(1) << 0) 1038 1039 /* 1040 * HI-VECTOR address for AArch32 state 1041 */ 1042 #define HI_VECTOR_BASE U(0xFFFF0000) 1043 1044 /* 1045 * TCR definitions 1046 */ 1047 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 1048 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 1049 #define TCR_EL1_IPS_SHIFT U(32) 1050 #define TCR_EL2_PS_SHIFT U(16) 1051 #define TCR_EL3_PS_SHIFT U(16) 1052 1053 #define TCR_TxSZ_MIN ULL(16) 1054 #define TCR_TxSZ_MAX ULL(39) 1055 #define TCR_TxSZ_MAX_TTST ULL(48) 1056 1057 #define TCR_T0SZ_SHIFT U(0) 1058 #define TCR_T1SZ_SHIFT U(16) 1059 1060 /* (internal) physical address size bits in EL3/EL1 */ 1061 #define TCR_PS_BITS_4GB ULL(0x0) 1062 #define TCR_PS_BITS_64GB ULL(0x1) 1063 #define TCR_PS_BITS_1TB ULL(0x2) 1064 #define TCR_PS_BITS_4TB ULL(0x3) 1065 #define TCR_PS_BITS_16TB ULL(0x4) 1066 #define TCR_PS_BITS_256TB ULL(0x5) 1067 1068 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 1069 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 1070 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 1071 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 1072 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 1073 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 1074 1075 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 1076 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 1077 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 1078 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 1079 1080 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 1081 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 1082 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 1083 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 1084 1085 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 1086 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 1087 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 1088 1089 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 1090 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 1091 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 1092 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 1093 1094 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 1095 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 1096 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 1097 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 1098 1099 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 1100 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 1101 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 1102 1103 #define TCR_TG0_SHIFT U(14) 1104 #define TCR_TG0_MASK ULL(3) 1105 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 1106 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 1107 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 1108 1109 #define TCR_HPD_BIT (ULL(1) << 24) 1110 #define TCR_HWU59_BIT (ULL(1) << 25) 1111 #define TCR_HWU60_BIT (ULL(1) << 26) 1112 #define TCR_HWU61_BIT (ULL(1) << 27) 1113 #define TCR_HWU62_BIT (ULL(1) << 28) 1114 1115 #define TCR_TG1_SHIFT U(30) 1116 #define TCR_TG1_MASK ULL(3) 1117 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 1118 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 1119 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 1120 1121 #define TCR_EPD0_BIT (ULL(1) << 7) 1122 #define TCR_EPD1_BIT (ULL(1) << 23) 1123 1124 #define MODE_SP_SHIFT U(0x0) 1125 #define MODE_SP_MASK U(0x1) 1126 #define MODE_SP_EL0 U(0x0) 1127 #define MODE_SP_ELX U(0x1) 1128 1129 #define MODE_RW_SHIFT U(0x4) 1130 #define MODE_RW_MASK U(0x1) 1131 #define MODE_RW_64 U(0x0) 1132 #define MODE_RW_32 U(0x1) 1133 1134 #define MODE_EL_SHIFT U(0x2) 1135 #define MODE_EL_MASK U(0x3) 1136 #define MODE_EL_WIDTH U(0x2) 1137 #define MODE_EL3 U(0x3) 1138 #define MODE_EL2 U(0x2) 1139 #define MODE_EL1 U(0x1) 1140 #define MODE_EL0 U(0x0) 1141 1142 #define MODE32_SHIFT U(0) 1143 #define MODE32_MASK U(0xf) 1144 #define MODE32_usr U(0x0) 1145 #define MODE32_fiq U(0x1) 1146 #define MODE32_irq U(0x2) 1147 #define MODE32_svc U(0x3) 1148 #define MODE32_mon U(0x6) 1149 #define MODE32_abt U(0x7) 1150 #define MODE32_hyp U(0xa) 1151 #define MODE32_und U(0xb) 1152 #define MODE32_sys U(0xf) 1153 1154 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 1155 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 1156 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 1157 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 1158 1159 #define SPSR_64(el, sp, daif) \ 1160 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 1161 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 1162 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 1163 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 1164 (~(SPSR_SSBS_BIT_AARCH64))) 1165 1166 #define SPSR_MODE32(mode, isa, endian, aif) \ 1167 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 1168 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 1169 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 1170 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 1171 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 1172 (~(SPSR_SSBS_BIT_AARCH32))) 1173 1174 /* 1175 * TTBR Definitions 1176 */ 1177 #define TTBR_CNP_BIT ULL(0x1) 1178 1179 /* 1180 * CTR_EL0 definitions 1181 */ 1182 #define CTR_CWG_SHIFT U(24) 1183 #define CTR_CWG_MASK U(0xf) 1184 #define CTR_ERG_SHIFT U(20) 1185 #define CTR_ERG_MASK U(0xf) 1186 #define CTR_DMINLINE_SHIFT U(16) 1187 #define CTR_DMINLINE_MASK U(0xf) 1188 #define CTR_L1IP_SHIFT U(14) 1189 #define CTR_L1IP_MASK U(0x3) 1190 #define CTR_IMINLINE_SHIFT U(0) 1191 #define CTR_IMINLINE_MASK U(0xf) 1192 1193 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 1194 1195 /* Physical timer control register bit fields shifts and masks */ 1196 #define CNTP_CTL_ENABLE_SHIFT U(0) 1197 #define CNTP_CTL_IMASK_SHIFT U(1) 1198 #define CNTP_CTL_ISTATUS_SHIFT U(2) 1199 1200 #define CNTP_CTL_ENABLE_MASK U(1) 1201 #define CNTP_CTL_IMASK_MASK U(1) 1202 #define CNTP_CTL_ISTATUS_MASK U(1) 1203 1204 /* Physical timer control macros */ 1205 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 1206 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 1207 1208 /* Exception Syndrome register bits and bobs */ 1209 #define ESR_EC_SHIFT U(26) 1210 #define ESR_EC_MASK U(0x3f) 1211 #define ESR_EC_LENGTH U(6) 1212 #define ESR_EC_WIDTH U(6) 1213 #define ESR_ISS_SHIFT U(0) 1214 #define ESR_ISS_LENGTH U(25) 1215 #define ESR_IL_BIT (U(1) << 25) 1216 #define EC_UNKNOWN U(0x0) 1217 #define EC_WFE_WFI U(0x1) 1218 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 1219 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 1220 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 1221 #define EC_AARCH32_CP14_LDC_STC U(0x6) 1222 #define EC_FP_SIMD U(0x7) 1223 #define EC_AARCH32_CP10_MRC U(0x8) 1224 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 1225 #define EC_ILLEGAL U(0xe) 1226 #define EC_AARCH32_SVC U(0x11) 1227 #define EC_AARCH32_HVC U(0x12) 1228 #define EC_AARCH32_SMC U(0x13) 1229 #define EC_AARCH64_SVC U(0x15) 1230 #define EC_AARCH64_HVC U(0x16) 1231 #define EC_AARCH64_SMC U(0x17) 1232 #define EC_AARCH64_SYS U(0x18) 1233 #define EC_IMP_DEF_EL3 U(0x1f) 1234 #define EC_IABORT_LOWER_EL U(0x20) 1235 #define EC_IABORT_CUR_EL U(0x21) 1236 #define EC_PC_ALIGN U(0x22) 1237 #define EC_DABORT_LOWER_EL U(0x24) 1238 #define EC_DABORT_CUR_EL U(0x25) 1239 #define EC_SP_ALIGN U(0x26) 1240 #define EC_AARCH32_FP U(0x28) 1241 #define EC_AARCH64_FP U(0x2c) 1242 #define EC_SERROR U(0x2f) 1243 #define EC_BRK U(0x3c) 1244 1245 /* 1246 * External Abort bit in Instruction and Data Aborts synchronous exception 1247 * syndromes. 1248 */ 1249 #define ESR_ISS_EABORT_EA_BIT U(9) 1250 1251 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 1252 1253 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 1254 #define RMR_RESET_REQUEST_SHIFT U(0x1) 1255 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 1256 1257 /******************************************************************************* 1258 * Definitions of register offsets, fields and macros for CPU system 1259 * instructions. 1260 ******************************************************************************/ 1261 1262 #define TLBI_ADDR_SHIFT U(12) 1263 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 1264 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 1265 1266 /******************************************************************************* 1267 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 1268 * system level implementation of the Generic Timer. 1269 ******************************************************************************/ 1270 #define CNTCTLBASE_CNTFRQ U(0x0) 1271 #define CNTNSAR U(0x4) 1272 #define CNTNSAR_NS_SHIFT(x) (x) 1273 1274 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 1275 #define CNTACR_RPCT_SHIFT U(0x0) 1276 #define CNTACR_RVCT_SHIFT U(0x1) 1277 #define CNTACR_RFRQ_SHIFT U(0x2) 1278 #define CNTACR_RVOFF_SHIFT U(0x3) 1279 #define CNTACR_RWVT_SHIFT U(0x4) 1280 #define CNTACR_RWPT_SHIFT U(0x5) 1281 1282 /******************************************************************************* 1283 * Definitions of register offsets and fields in the CNTBaseN Frame of the 1284 * system level implementation of the Generic Timer. 1285 ******************************************************************************/ 1286 /* Physical Count register. */ 1287 #define CNTPCT_LO U(0x0) 1288 /* Counter Frequency register. */ 1289 #define CNTBASEN_CNTFRQ U(0x10) 1290 /* Physical Timer CompareValue register. */ 1291 #define CNTP_CVAL_LO U(0x20) 1292 /* Physical Timer Control register. */ 1293 #define CNTP_CTL U(0x2c) 1294 1295 /* PMCR_EL0 definitions */ 1296 #define PMCR_EL0_RESET_VAL U(0x0) 1297 #define PMCR_EL0_N_SHIFT U(11) 1298 #define PMCR_EL0_N_MASK U(0x1f) 1299 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1300 #define PMCR_EL0_LP_BIT (U(1) << 7) 1301 #define PMCR_EL0_LC_BIT (U(1) << 6) 1302 #define PMCR_EL0_DP_BIT (U(1) << 5) 1303 #define PMCR_EL0_X_BIT (U(1) << 4) 1304 #define PMCR_EL0_D_BIT (U(1) << 3) 1305 #define PMCR_EL0_C_BIT (U(1) << 2) 1306 #define PMCR_EL0_P_BIT (U(1) << 1) 1307 #define PMCR_EL0_E_BIT (U(1) << 0) 1308 1309 /******************************************************************************* 1310 * Definitions for system register interface to SVE 1311 ******************************************************************************/ 1312 #define ZCR_EL3 S3_6_C1_C2_0 1313 #define ZCR_EL2 S3_4_C1_C2_0 1314 1315 /* ZCR_EL3 definitions */ 1316 #define ZCR_EL3_LEN_MASK UL(0xf) 1317 1318 /******************************************************************************* 1319 * Definitions for system register interface to SME as needed in EL3 1320 ******************************************************************************/ 1321 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1322 #define SMCR_EL3 S3_6_C1_C2_6 1323 #define SVCR S3_3_C4_C2_2 1324 1325 /* ID_AA64SMFR0_EL1 definitions */ 1326 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1327 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1328 #define SME_FA64_IMPLEMENTED U(0x1) 1329 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1330 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1331 #define SME_INST_IMPLEMENTED ULL(0x0) 1332 #define SME2_INST_IMPLEMENTED ULL(0x1) 1333 1334 /* SMCR_ELx definitions */ 1335 #define SMCR_ELX_LEN_SHIFT U(0) 1336 #define SMCR_ELX_LEN_MAX U(0x1ff) 1337 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1338 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1339 1340 /******************************************************************************* 1341 * Definitions of MAIR encodings for device and normal memory 1342 ******************************************************************************/ 1343 /* 1344 * MAIR encodings for device memory attributes. 1345 */ 1346 #define MAIR_DEV_nGnRnE ULL(0x0) 1347 #define MAIR_DEV_nGnRE ULL(0x4) 1348 #define MAIR_DEV_nGRE ULL(0x8) 1349 #define MAIR_DEV_GRE ULL(0xc) 1350 1351 /* 1352 * MAIR encodings for normal memory attributes. 1353 * 1354 * Cache Policy 1355 * WT: Write Through 1356 * WB: Write Back 1357 * NC: Non-Cacheable 1358 * 1359 * Transient Hint 1360 * NTR: Non-Transient 1361 * TR: Transient 1362 * 1363 * Allocation Policy 1364 * RA: Read Allocate 1365 * WA: Write Allocate 1366 * RWA: Read and Write Allocate 1367 * NA: No Allocation 1368 */ 1369 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1370 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1371 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1372 #define MAIR_NORM_NC ULL(0x4) 1373 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1374 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1375 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1376 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1377 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1378 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1379 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1380 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1381 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1382 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1383 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1384 1385 #define MAIR_NORM_OUTER_SHIFT U(4) 1386 1387 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1388 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1389 1390 /* PAR_EL1 fields */ 1391 #define PAR_F_SHIFT U(0) 1392 #define PAR_F_MASK ULL(0x1) 1393 1394 #define PAR_D128_ADDR_MASK GENMASK(55, 12) /* 44-bits-wide page address */ 1395 #define PAR_ADDR_MASK GENMASK(51, 12) /* 40-bits-wide page address */ 1396 1397 /******************************************************************************* 1398 * Definitions for system register interface to SPE 1399 ******************************************************************************/ 1400 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1401 1402 /******************************************************************************* 1403 * Definitions for system register interface, shifts and masks for MPAM 1404 ******************************************************************************/ 1405 #define MPAMIDR_EL1 S3_0_C10_C4_4 1406 #define MPAM2_EL2 S3_4_C10_C5_0 1407 #define MPAMHCR_EL2 S3_4_C10_C4_0 1408 #define MPAM3_EL3 S3_6_C10_C5_0 1409 1410 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1411 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1412 /******************************************************************************* 1413 * Definitions for system register interface to AMU for FEAT_AMUv1 1414 ******************************************************************************/ 1415 #define AMCR_EL0 S3_3_C13_C2_0 1416 #define AMCFGR_EL0 S3_3_C13_C2_1 1417 #define AMCGCR_EL0 S3_3_C13_C2_2 1418 #define AMUSERENR_EL0 S3_3_C13_C2_3 1419 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1420 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1421 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1422 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1423 1424 /* Activity Monitor Group 0 Event Counter Registers */ 1425 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1426 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1427 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1428 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1429 1430 /* Activity Monitor Group 0 Event Type Registers */ 1431 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1432 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1433 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1434 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1435 1436 /* Activity Monitor Group 1 Event Counter Registers */ 1437 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1438 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1439 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1440 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1441 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1442 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1443 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1444 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1445 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1446 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1447 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1448 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1449 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1450 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1451 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1452 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1453 1454 /* Activity Monitor Group 1 Event Type Registers */ 1455 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1456 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1457 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1458 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1459 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1460 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1461 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1462 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1463 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1464 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1465 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1466 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1467 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1468 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1469 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1470 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1471 1472 /* AMCNTENSET0_EL0 definitions */ 1473 #define AMCNTENSET0_EL0_Pn_ALWAYS_ON ULL(0x3) 1474 #define AMCNTENSET0_EL0_Pn_CONTEXTED ULL(0xc) 1475 #define AMCNTENSET0_EL0_Pn_ALL ULL(0xf) 1476 1477 /* AMCNTENSET1_EL0 definitions */ 1478 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1479 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1480 1481 /* AMCNTENCLR0_EL0 definitions */ 1482 #define AMCNTENCLR0_EL0_Pn_ALWAYS_ON ULL(0x3) 1483 #define AMCNTENCLR0_EL0_Pn_CONTEXTED ULL(0xc) 1484 #define AMCNTENCLR0_EL0_Pn_ALL ULL(0xf) 1485 1486 /* AMCNTENCLR1_EL0 definitions */ 1487 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1488 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1489 1490 /* AMCFGR_EL0 definitions */ 1491 #define AMCFGR_EL0_NCG_SHIFT U(28) 1492 #define AMCFGR_EL0_NCG_MASK U(0xf) 1493 #define AMCFGR_EL0_N_SHIFT U(0) 1494 #define AMCFGR_EL0_N_MASK U(0xff) 1495 1496 /* AMCGCR_EL0 definitions */ 1497 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1498 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1499 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1500 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1501 1502 /* MPAM register definitions */ 1503 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1504 #define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62) 1505 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1506 #define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT 1507 1508 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1509 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1510 1511 #define MPAMIDR_HAS_BW_CTRL_BIT (ULL(1) << 56) 1512 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1513 1514 /* MPAM_PE_BW_CTRL register definitions */ 1515 #define MPAMBW2_EL2 S3_4_C10_C5_4 1516 #define MPAMBW2_EL2_HW_SCALE_ENABLE_BIT (ULL(1) << 63) 1517 #define MPAMBW2_EL2_ENABLED_BIT (ULL(1) << 62) 1518 #define MPAMBW2_EL2_HARDLIM_BIT (ULL(1) << 61) 1519 #define MPAMBW2_EL2_NTRAP_MPAMBWIDR_EL1_BIT (ULL(1) << 52) 1520 #define MPAMBW2_EL2_NTRAP_MPAMBW0_EL1_BIT (ULL(1) << 51) 1521 #define MPAMBW2_EL2_NTRAP_MPAMBW1_EL1_BIT (ULL(1) << 50) 1522 #define MPAMBW2_EL2_NTRAP_MPAMBWSM_EL1_BIT (ULL(1) << 49) 1523 1524 #define MPAMBW3_EL3 S3_6_C10_C5_4 1525 #define MPAMBW3_EL3_HW_SCALE_ENABLE_BIT (ULL(1) << 63) 1526 #define MPAMBW3_EL3_ENABLED_BIT (ULL(1) << 62) 1527 #define MPAMBW3_EL3_HARDLIM_BIT (ULL(1) << 61) 1528 #define MPAMBW3_EL3_NTRAPLOWER_BIT (ULL(1) << 49) 1529 1530 /******************************************************************************* 1531 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1532 ******************************************************************************/ 1533 1534 /* Definition for register defining which virtual offsets are implemented. */ 1535 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1536 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1537 #define AMCG1IDR_CTR_SHIFT U(0) 1538 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1539 #define AMCG1IDR_VOFF_SHIFT U(16) 1540 1541 /* New bit added to AMCR_EL0 */ 1542 #define AMCR_CG1RZ_SHIFT U(17) 1543 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1544 1545 /* 1546 * Definitions for virtual offset registers for architected activity monitor 1547 * event counters. 1548 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1549 */ 1550 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1551 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1552 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1553 1554 /* 1555 * Definitions for virtual offset registers for auxiliary activity monitor event 1556 * counters. 1557 */ 1558 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1559 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1560 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1561 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1562 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1563 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1564 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1565 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1566 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1567 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1568 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1569 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1570 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1571 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1572 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1573 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1574 1575 /******************************************************************************* 1576 * Realm management extension register definitions 1577 ******************************************************************************/ 1578 #define GPCCR_EL3 S3_6_C2_C1_6 1579 #define GPTBR_EL3 S3_6_C2_C1_4 1580 1581 #define SCXTNUM_EL2 S3_4_C13_C0_7 1582 #define SCXTNUM_EL1 S3_0_C13_C0_7 1583 #define SCXTNUM_EL0 S3_3_C13_C0_7 1584 1585 /******************************************************************************* 1586 * RAS system registers 1587 ******************************************************************************/ 1588 #define DISR_EL1 S3_0_C12_C1_1 1589 #define DISR_A_BIT U(31) 1590 1591 #define ERRIDR_EL1 S3_0_C5_C3_0 1592 #define ERRIDR_MASK U(0xffff) 1593 1594 #define ERRSELR_EL1 S3_0_C5_C3_1 1595 1596 /* System register access to Standard Error Record registers */ 1597 #define ERXFR_EL1 S3_0_C5_C4_0 1598 #define ERXCTLR_EL1 S3_0_C5_C4_1 1599 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1600 #define ERXADDR_EL1 S3_0_C5_C4_3 1601 #define ERXPFGF_EL1 S3_0_C5_C4_4 1602 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1603 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1604 #define ERXMISC0_EL1 S3_0_C5_C5_0 1605 #define ERXMISC1_EL1 S3_0_C5_C5_1 1606 1607 #define ERXCTLR_ED_SHIFT U(0) 1608 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1609 #define ERXCTLR_UE_BIT (U(1) << 4) 1610 1611 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1612 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1613 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1614 1615 /******************************************************************************* 1616 * Armv8.3 Pointer Authentication Registers 1617 ******************************************************************************/ 1618 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1619 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1620 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1621 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1622 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1623 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1624 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1625 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1626 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1627 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1628 1629 /******************************************************************************* 1630 * Armv8.4 Data Independent Timing Registers 1631 ******************************************************************************/ 1632 #define DIT S3_3_C4_C2_5 1633 #define DIT_BIT BIT(24) 1634 1635 /******************************************************************************* 1636 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1637 ******************************************************************************/ 1638 #define SSBS S3_3_C4_C2_6 1639 1640 /******************************************************************************* 1641 * Armv8.5 - Memory Tagging Extension Registers 1642 ******************************************************************************/ 1643 #define TFSRE0_EL1 S3_0_C5_C6_1 1644 #define TFSR_EL1 S3_0_C5_C6_0 1645 #define RGSR_EL1 S3_0_C1_C0_5 1646 #define GCR_EL1 S3_0_C1_C0_6 1647 1648 #define GCR_EL1_RRND_BIT (UL(1) << 16) 1649 1650 /******************************************************************************* 1651 * Armv8.5 - Random Number Generator Registers 1652 ******************************************************************************/ 1653 #define RNDR S3_3_C2_C4_0 1654 #define RNDRRS S3_3_C2_C4_1 1655 1656 /******************************************************************************* 1657 * FEAT_HCX - Extended Hypervisor Configuration Register 1658 ******************************************************************************/ 1659 #define HCRX_EL2 S3_4_C1_C2_2 1660 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1661 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1662 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1663 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1664 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1665 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1666 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1667 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1668 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1669 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1670 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1671 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1672 #define HCRX_EL2_INIT_VAL ULL(0x0) 1673 1674 /******************************************************************************* 1675 * FEAT_FGT - Definitions for Fine-Grained Trap registers 1676 ******************************************************************************/ 1677 #define HFGITR_EL2_INIT_VAL ULL(0x180000000000000) 1678 #define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000) 1679 #define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000) 1680 1681 /******************************************************************************* 1682 * FEAT_TCR2 - Extended Translation Control Registers 1683 ******************************************************************************/ 1684 #define TCR2_EL1 S3_0_C2_C0_3 1685 #define TCR2_EL2 S3_4_C2_C0_3 1686 1687 #define TCR2_EL2_INIT_VAL ULL(0) 1688 1689 /******************************************************************************* 1690 * Permission indirection and overlay Registers 1691 ******************************************************************************/ 1692 1693 #define PIRE0_EL1 S3_0_C10_C2_2 1694 #define PIRE0_EL2 S3_4_C10_C2_2 1695 #define PIR_EL1 S3_0_C10_C2_3 1696 #define PIR_EL2 S3_4_C10_C2_3 1697 #define POR_EL1 S3_0_C10_C2_4 1698 #define POR_EL2 S3_4_C10_C2_4 1699 #define S2PIR_EL2 S3_4_C10_C2_5 1700 #define S2POR_EL1 S3_0_C10_C2_5 1701 1702 /******************************************************************************* 1703 * FEAT_GCS - Guarded Control Stack Registers 1704 ******************************************************************************/ 1705 #define GCSCR_EL2 S3_4_C2_C5_0 1706 #define GCSPR_EL2 S3_4_C2_C5_1 1707 #define GCSCR_EL1 S3_0_C2_C5_0 1708 #define GCSCRE0_EL1 S3_0_C2_C5_2 1709 #define GCSPR_EL1 S3_0_C2_C5_1 1710 #define GCSPR_EL0 S3_3_C2_C5_1 1711 1712 #define GCSCR_EXLOCK_EN_BIT (UL(1) << 6) 1713 1714 /******************************************************************************* 1715 * FEAT_TRF - Trace Filter Control Registers 1716 ******************************************************************************/ 1717 #define TRFCR_EL2 S3_4_C1_C2_1 1718 #define TRFCR_EL1 S3_0_C1_C2_1 1719 1720 /******************************************************************************* 1721 * FEAT_STEP2 - Step2 registers 1722 ******************************************************************************/ 1723 #define MDSTEPOP_EL1 S2_0_C0_C5_2 1724 1725 /******************************************************************************* 1726 * FEAT_THE - Translation Hardening Extension Registers 1727 ******************************************************************************/ 1728 #define RCWMASK_EL1 S3_0_C13_C0_6 1729 #define RCWSMASK_EL1 S3_0_C13_C0_3 1730 1731 /******************************************************************************* 1732 * FEAT_SCTLR2 - Extension to SCTLR_ELx Registers 1733 ******************************************************************************/ 1734 #define SCTLR2_EL3 S3_6_C1_C0_3 1735 #define SCTLR2_EL2 S3_4_C1_C0_3 1736 #define SCTLR2_EL1 S3_0_C1_C0_3 1737 1738 /******************************************************************************* 1739 * FEAT_BRBE - Branch Record Buffer Extension Registers 1740 ******************************************************************************/ 1741 #define BRBCR_EL2 S2_4_C9_C0_0 1742 1743 /******************************************************************************* 1744 * FEAT_LS64_ACCDATA - LoadStore64B with status data 1745 ******************************************************************************/ 1746 #define ACCDATA_EL1 S3_0_C13_C0_5 1747 1748 /******************************************************************************* 1749 * Definitions for DynamicIQ Shared Unit registers 1750 ******************************************************************************/ 1751 #define CLUSTERPWRDN_EL1 S3_0_C15_C3_6 1752 1753 /******************************************************************************* 1754 * FEAT_FPMR - Floating point Mode Register 1755 ******************************************************************************/ 1756 #define FPMR S3_3_C4_C4_2 1757 1758 /* CLUSTERPWRDN_EL1 register definitions */ 1759 #define DSU_CLUSTER_PWR_OFF 0 1760 #define DSU_CLUSTER_PWR_ON 1 1761 #define DSU_CLUSTER_PWR_MASK U(1) 1762 #define DSU_CLUSTER_MEM_RET BIT(1) 1763 1764 /* CLUSTERPMMDCR register definitions */ 1765 #define CLUSTERPMMDCR_SPME U(1) 1766 1767 /******************************************************************************* 1768 * Definitions for CPU Power/Performance Management registers 1769 ******************************************************************************/ 1770 1771 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1772 #define CPUPPMCR_EL3_MPMMPINCTL_BIT BIT(0) 1773 1774 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1775 #define CPUMPMMCR_EL3_MPMM_EN_BIT BIT(0) 1776 1777 /* alternative system register encoding for the "sb" speculation barrier */ 1778 #define SYSREG_SB S0_3_C3_C0_7 1779 1780 #define CLUSTERPMCR_EL1 S3_0_C15_C5_0 1781 #define CLUSTERPMCNTENSET_EL1 S3_0_C15_C5_1 1782 #define CLUSTERPMCCNTR_EL1 S3_0_C15_C6_0 1783 #define CLUSTERPMOVSSET_EL1 S3_0_C15_C5_3 1784 #define CLUSTERPMOVSCLR_EL1 S3_0_C15_C5_4 1785 #define CLUSTERPMSELR_EL1 S3_0_C15_C5_5 1786 #define CLUSTERPMXEVTYPER_EL1 S3_0_C15_C6_1 1787 #define CLUSTERPMXEVCNTR_EL1 S3_0_C15_C6_2 1788 #define CLUSTERPMMDCR_EL3 S3_6_C15_C6_3 1789 1790 #define CLUSTERPMCR_E_BIT BIT(0) 1791 #define CLUSTERPMCR_N_SHIFT U(11) 1792 #define CLUSTERPMCR_N_MASK U(0x1f) 1793 1794 /******************************************************************************* 1795 * FEAT_MEC - Memory Encryption Contexts 1796 ******************************************************************************/ 1797 #define MECIDR_EL2 S3_4_C10_C8_7 1798 #define MECIDR_EL2_MECIDWidthm1_MASK U(0xf) 1799 #define MECIDR_EL2_MECIDWidthm1_SHIFT U(0) 1800 1801 /****************************************************************************** 1802 * FEAT_FGWTE3 - Fine Grained Write Trap 1803 ******************************************************************************/ 1804 #define FGWTE3_EL3 S3_6_C1_C1_5 1805 1806 /* FGWTE3_EL3 Defintions */ 1807 #define FGWTE3_EL3_GPCBW_EL3_BIT (U(1) << 22) 1808 #define FGWTE3_EL3_VBAR_EL3_BIT (U(1) << 21) 1809 #define FGWTE3_EL3_TTBR0_EL3_BIT (U(1) << 20) 1810 #define FGWTE3_EL3_TPIDR_EL3_BIT (U(1) << 19) 1811 #define FGWTE3_EL3_TCR_EL3_BIT (U(1) << 18) 1812 #define FGWTE3_EL3_SPMROOTCR_EL3_BIT (U(1) << 17) 1813 #define FGWTE3_EL3_SCTLR2_EL3_BIT (U(1) << 16) 1814 #define FGWTE3_EL3_SCTLR_EL3_BIT (U(1) << 15) 1815 #define FGWTE3_EL3_PIR_EL3_BIT (U(1) << 14) 1816 #define FGWTE3_EL3_MECID_RL_A_EL3_BIT (U(1) << 12) 1817 #define FGWTE3_EL3_MAIR2_EL3_BIT (U(1) << 10) 1818 #define FGWTE3_EL3_MAIR_EL3_BIT (U(1) << 9) 1819 #define FGWTE3_EL3_GPTBR_EL3_BIT (U(1) << 8) 1820 #define FGWTE3_EL3_GPCCR_EL3_BIT (U(1) << 7) 1821 #define FGWTE3_EL3_GCSPR_EL3_BIT (U(1) << 6) 1822 #define FGWTE3_EL3_GCSCR_EL3_BIT (U(1) << 5) 1823 #define FGWTE3_EL3_AMAIR2_EL3_BIT (U(1) << 4) 1824 #define FGWTE3_EL3_AMAIR_EL3_BIT (U(1) << 3) 1825 #define FGWTE3_EL3_AFSR1_EL3_BIT (U(1) << 2) 1826 #define FGWTE3_EL3_AFSR0_EL3_BIT (U(1) << 1) 1827 #define FGWTE3_EL3_ACTLR_EL3_BIT (U(1) << 0) 1828 1829 #define FGWTE3_EL3_EARLY_INIT_VAL ( \ 1830 FGWTE3_EL3_GPCBW_EL3_BIT | \ 1831 FGWTE3_EL3_VBAR_EL3_BIT | \ 1832 FGWTE3_EL3_TTBR0_EL3_BIT | \ 1833 FGWTE3_EL3_SPMROOTCR_EL3_BIT | \ 1834 FGWTE3_EL3_SCTLR2_EL3_BIT | \ 1835 FGWTE3_EL3_PIR_EL3_BIT | \ 1836 FGWTE3_EL3_MECID_RL_A_EL3_BIT | \ 1837 FGWTE3_EL3_MAIR2_EL3_BIT | \ 1838 FGWTE3_EL3_MAIR_EL3_BIT | \ 1839 FGWTE3_EL3_GCSPR_EL3_BIT | \ 1840 FGWTE3_EL3_GCSCR_EL3_BIT | \ 1841 FGWTE3_EL3_AMAIR2_EL3_BIT | \ 1842 FGWTE3_EL3_AMAIR_EL3_BIT | \ 1843 FGWTE3_EL3_AFSR1_EL3_BIT | \ 1844 FGWTE3_EL3_AFSR0_EL3_BIT) 1845 1846 #if HW_ASSISTED_COHERENCY 1847 #define FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT FGWTE3_EL3_SCTLR_EL3_BIT 1848 #else 1849 #define FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT 0 1850 #endif 1851 1852 #if !(CRASH_REPORTING) 1853 #define FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT FGWTE3_EL3_TPIDR_EL3_BIT 1854 #else 1855 #define FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT 0 1856 #endif 1857 1858 #define FGWTE3_EL3_LATE_INIT_VAL ( \ 1859 FGWTE3_EL3_EARLY_INIT_VAL | \ 1860 FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT | \ 1861 FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT | \ 1862 FGWTE3_EL3_TCR_EL3_BIT | \ 1863 FGWTE3_EL3_GPTBR_EL3_BIT | \ 1864 FGWTE3_EL3_GPCCR_EL3_BIT | \ 1865 FGWTE3_EL3_ACTLR_EL3_BIT) 1866 1867 #endif /* ARCH_H */ 1868