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Searched refs:DVFSRC_RSRV_0 (Results 1 – 5 of 5) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_vcorefs_reg.h112 #define DVFSRC_RSRV_0 (DVFSRC_BASE + 0x280) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_vcorefs.h185 #define DVFSRC_RSRV_0 (DVFSRC_BASE + 0x600) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_vcorefs.h198 #define DVFSRC_RSRV_0 (DVFSRC_BASE + 0x600) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_vcore_dvfsrc_plat.c192 rsrv0 = mmio_read_32(DVFSRC_RSRV_0); in spm_vcorefs_vcore_setting()
H A Dmt_spm_vcorefs_reg.h130 #define DVFSRC_RSRV_0 (DVFSRC_BASE + 0x280) macro