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Searched refs:DVFSRC_RECORD_0_5 (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_vcorefs.h98 #define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0xB04) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_vcorefs.h268 #define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0xB04) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_vcorefs.h282 #define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0xB04) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm_vcorefs_reg.h205 #define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0x3CC) macro