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Searched refs:DVFSRC_RECORD_0_2 (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_vcorefs.h95 #define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0xAF8) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_vcorefs.h265 #define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0xAF8) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_vcorefs.h279 #define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0xAF8) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm_vcorefs_reg.h202 #define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0x3C0) macro