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Searched refs:DVFSRC_DDR_QOS5 (Results 1 – 10 of 10) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_vcore_dvfsrc_plat_def.h30 { DVFSRC_DDR_QOS5, 0x000000AF },
H A Dmt_spm_vcorefs_reg.h142 #define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0x2FC) macro
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_vcorefs.h119 #define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18) macro
H A Dmt_spm_vcorefs.c75 { DVFSRC_DDR_QOS5, 0x00000066 },
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_vcore_dvfsrc_plat_def.h58 { DVFSRC_DDR_QOS5, 0x000001F9 },
H A Dmt_spm_vcorefs_reg.h155 #define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0x2FC) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_vcorefs.c40 { DVFSRC_DDR_QOS5, 0x00000066 },
H A Dmt_spm_vcorefs.h303 #define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_vcorefs.c231 {DVFSRC_DDR_QOS5, 0x00000077},
H A Dmt_spm_vcorefs.h289 #define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18) macro