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Searched refs:DVFSRC_95MD_SCEN_BW0 (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_vcorefs_reg.h102 #define DVFSRC_95MD_SCEN_BW0 (DVFSRC_BASE + 0x258) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_vcorefs.h175 #define DVFSRC_95MD_SCEN_BW0 (DVFSRC_BASE + 0x524) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_vcorefs.h188 #define DVFSRC_95MD_SCEN_BW0 (DVFSRC_BASE + 0x524) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm_vcorefs_reg.h120 #define DVFSRC_95MD_SCEN_BW0 (DVFSRC_BASE + 0x258) macro