Searched refs:DSUGRF_BASE (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/ |
| H A D | pm_pd_regs.c | 172 REG_REGION(0x00, 0x18, 4, DSUGRF_BASE, WMSK_VAL),
173 REG_REGION(0x20, 0x20, 4, DSUGRF_BASE, WMSK_VAL),
174 REG_REGION(0x28, 0x30, 4, DSUGRF_BASE, WMSK_VAL),
175 REG_REGION(0x38, 0x38, 4, DSUGRF_BASE, WMSK_VAL),
500 mmio_write_32(DSUGRF_BASE + 0x18, BITS_WITH_WMASK(1, 0x1, 14)); in pd_dsu_core_restore()
505 mmio_write_32(DSUGRF_BASE + 0x18, BITS_WITH_WMASK(0, 0x1, 14)); in pd_dsu_core_restore()
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| /rk3399_ARM-atf/plat/rockchip/rk3588/ |
| H A D | rk3588_def.h | 37 #define DSUGRF_BASE 0xfd598000 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/ |
| H A D | rk3588_clk.c | 855 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON2, in clk_dsu_set_rate()
858 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON0_L, in clk_dsu_set_rate()
861 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON0_H, in clk_dsu_set_rate()
864 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON1, in clk_dsu_set_rate()
867 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON0_L, in clk_dsu_set_rate()
870 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON0_L, in clk_dsu_set_rate()
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