Searched refs:DRAM_MEM_1_START (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/imx/imx8ulp/xrdc/ |
| H A D | xrdc_config.h | 49 #define DRAM_MEM_1_START (BL32_BASE) macro
53 #define DRAM_MEM_2_START (DRAM_MEM_1_START + DRAM_MEM_1_SIZE)
60 #define DRAM_MEM_2_START (DRAM_MEM_1_START + DRAM_MEM_1_SIZE)
76 …{ 4, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, {0, 1, 0, 0, 0, 0, 0, 1}, {0xfc0, 0} }, /* TEE DRAM for…
84 …{ 5, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, {0, 1, 0, 0, 0, 0, 0, 0}, {0xfc0, 0} }, /* TEE DRAM for…
93 …{ 6, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, {1, 1, 0, 1, 1, 0, 1, 1}, {0xfc0, 0} }, /* TEE DRAM for…
99 …{ 6, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, {1, 1, 0, 1, 1, 0, 1, 1}, {0xfc0, 0} }, /* TEE DRAM for…
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| /rk3399_ARM-atf/plat/imx/imx93/ |
| H A D | trdc_config.h | 205 #define DRAM_MEM_1_START (BL32_BASE) macro
208 #define DRAM_MEM_2_START (DRAM_MEM_1_START + DRAM_MEM_1_SIZE)
226 { 0, 3, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, 1, true }, /* MRC0 DRAM for A55 DID3 */
227 { 0, 5, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, 0, true }, /* MRC0 DRAM for USDHC1 DID5 */
228 { 0, 6, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, 0, true }, /* MRC0 DRAM for USDHC2 DID6 */
229 { 0, 7, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, 0, true }, /* MRC0 DRAM for eDMA DID7 */
230 { 0, 10, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, 0, true }, /* MRC0 DRAM for SoC masters DID10 */
231 { 0, 11, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, 0, true }, /* MRC0 DRAM for USB DID11 */
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