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Searched refs:DIV_ROUND_UP (Results 1 – 5 of 5) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/common/scmi/
H A Drockchip_common_clock.c25 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) macro
85 div = DIV_ROUND_UP(parent_rate, rate); in clk_scmi_common_set_rate()
108 div = DIV_ROUND_UP(parent_rate, rate); in clk_scmi_common_set_rate()
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/scmi/
H A Drk3568_clk.c23 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) macro
415 div = DIV_ROUND_UP(rate, 300000000); in clk_cpu_set_rate()
421 div = DIV_ROUND_UP(rate, 300000000); in clk_cpu_set_rate()
514 div = DIV_ROUND_UP(GPLL_RATE, rate); in clk_gpu_set_rate()
580 div = DIV_ROUND_UP(GPLL_RATE, rate); in clk_npu_set_rate()
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/
H A Drk3588_clk.c28 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) macro
346 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; in clk_cpul_set_rate()
515 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; in clk_cpub01_set_rate()
684 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; in clk_cpub23_set_rate()
880 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; in clk_dsu_set_rate()
981 div = DIV_ROUND_UP(GPLL_RATE, rate); in clk_gpu_set_rate()
1080 div = DIV_ROUND_UP(GPLL_RATE, rate); in clk_npu_set_rate()
1134 div = DIV_ROUND_UP(SPLL_RATE, rate); in clk_scmi_sbus_set_rate()
1161 div = DIV_ROUND_UP(SPLL_RATE, rate); in clk_scmi_pclk_sbus_set_rate()
1195 div = DIV_ROUND_UP(OSC_HZ, rate); in clk_scmi_cclk_sdmmc_set_rate()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3576/scmi/
H A Drk3576_clk.c28 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) macro
458 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; in clk_cpul_set_rate()
622 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; in clk_cpub_set_rate()
881 div = DIV_ROUND_UP(GPLL_RATE, rate); in clk_gpu_set_rate()
983 div = DIV_ROUND_UP(GPLL_RATE, rate); in clk_npu_set_rate()
/rk3399_ARM-atf/docs/
H A Dchange-log.md11158 - socionext/uniphier: Replace DIV_ROUND_UP() with div_round_up() from