Searched refs:DENALI_CTL_147 (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/plat/renesas/rza/soc/rza3m/include/ |
| H A D | ddr_mc_if.h | 38 #define DDRMC_R022 DENALI_CTL_147
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| H A D | ddr_mc_regs.h | 180 #define DENALI_CTL_147 0x024C macro
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| /rk3399_ARM-atf/plat/imx/imx8ulp/ |
| H A D | dram.c | 59 #define DENALI_CTL_147 U(0x24c) macro
228 dram_timing_cfg->auto_lp_cfg[1] = mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_147); in dram_lp_auto_disable()
242 mmio_clrbits_32(IMX_DDRC_BASE + DENALI_CTL_147, LP_AUTO_EXIT_EN); in dram_lp_auto_disable()
267 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_147, dram_timing_cfg->auto_lp_cfg[1]); in dram_lp_auto_enable()
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| /rk3399_ARM-atf/plat/renesas/rza/soc/rza3m/drivers/ddr/ |
| H A D | param_mc_C-011_D3-01-1.c | 87 { DENALI_CTL_146, 0x00000000 }, { DENALI_CTL_147, 0x00000000 },
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| H A D | param_mc_C-011_D3-02-1.c | 87 { DENALI_CTL_146, 0x00000000 }, { DENALI_CTL_147, 0x00000000 },
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