Searched refs:DENALI_CTL_146 (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/plat/imx/imx8ulp/ |
| H A D | dram.c | 30 #define DENALI_CTL_146 U(0x248) macro
221 lp_auto_en = (mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_146) & (LP_AUTO_ENTRY_EN << 24)); in dram_lp_auto_disable()
229 dram_timing_cfg->auto_lp_cfg[2] = mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_146); in dram_lp_auto_disable()
233 mmio_clrbits_32(IMX_DDRC_BASE + DENALI_CTL_146, LP_AUTO_ENTRY_EN << 24); in dram_lp_auto_disable()
237 while ((mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_146) & in dram_lp_auto_disable()
253 while ((mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_146) & in dram_lp_auto_enable()
269 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_146, dram_timing_cfg->auto_lp_cfg[2]); in dram_lp_auto_enable()
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| /rk3399_ARM-atf/plat/renesas/rza/soc/rza3m/include/ |
| H A D | ddr_mc_if.h | 37 #define DDRMC_R021 DENALI_CTL_146
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| H A D | ddr_mc_regs.h | 179 #define DENALI_CTL_146 0x0248 macro
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| /rk3399_ARM-atf/plat/renesas/rza/soc/rza3m/drivers/ddr/ |
| H A D | param_mc_C-011_D3-01-1.c | 87 { DENALI_CTL_146, 0x00000000 }, { DENALI_CTL_147, 0x00000000 },
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| H A D | param_mc_C-011_D3-02-1.c | 87 { DENALI_CTL_146, 0x00000000 }, { DENALI_CTL_147, 0x00000000 },
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