Searched refs:DENALI_CTL_144 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/imx/imx8ulp/ |
| H A D | dram.c | 29 #define DENALI_CTL_144 U(0x240) macro
227 dram_timing_cfg->auto_lp_cfg[0] = mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_144); in dram_lp_auto_disable()
266 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_144, dram_timing_cfg->auto_lp_cfg[0]); in dram_lp_auto_enable()
292 mmio_setbits_32(IMX_DDRC_BASE + DENALI_CTL_144, BIT(3) << LPI_WAKEUP_EN_SHIFT); in dram_enter_self_refresh()
333 mmio_setbits_32(IMX_DDRC_BASE + DENALI_CTL_144, BIT(3) << LPI_WAKEUP_EN_SHIFT); in dram_enter_retention()
491 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_144, 0x00002D00); in dram_exit_retention()
494 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_144, 0x1); in dram_exit_retention()
649 ddr_ctl_144 = mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_144); in lpddr4_dfs()
650 mmio_setbits_32(IMX_DDRC_BASE + DENALI_CTL_144, LPI_WAKEUP_EN); in lpddr4_dfs()
686 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_144, ddr_ctl_144); in lpddr4_dfs()
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| /rk3399_ARM-atf/plat/renesas/rza/soc/rza3m/drivers/ddr/ |
| H A D | param_mc_C-011_D3-01-1.c | 86 { DENALI_CTL_144, 0x00000000 }, { DENALI_CTL_145, 0x00000000 },
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| H A D | param_mc_C-011_D3-02-1.c | 86 { DENALI_CTL_144, 0x00000000 }, { DENALI_CTL_145, 0x00000000 },
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| /rk3399_ARM-atf/plat/renesas/rza/soc/rza3m/include/ |
| H A D | ddr_mc_regs.h | 177 #define DENALI_CTL_144 0x0240 macro
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