Searched refs:DENALI_CTL_00 (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/plat/renesas/rza/soc/rza3m/include/ |
| H A D | ddr_mc_if.h | 16 #define DDRMC_R000 DENALI_CTL_00
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| H A D | ddr_mc_regs.h | 33 #define DENALI_CTL_00 0x0000 macro
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| /rk3399_ARM-atf/plat/imx/imx8ulp/ |
| H A D | dram.c | 44 #define DENALI_CTL_00 U(0x0) macro
358 dram_class = mmio_read_32(IMX_DDRC_BASE + DENALI_CTL_00); in dram_enter_retention()
522 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_00, 0x00000b01); in dram_exit_retention()
528 mmio_write_32(IMX_DDRC_BASE + DENALI_CTL_00, 0x00000701); in dram_exit_retention()
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| /rk3399_ARM-atf/plat/renesas/rza/soc/rza3m/drivers/ddr/ |
| H A D | param_mc_C-011_D3-01-1.c | 14 { DENALI_CTL_00, 0x00000600 }, { DENALI_CTL_01, 0x00000000 },
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| H A D | param_mc_C-011_D3-02-1.c | 14 { DENALI_CTL_00, 0x00000600 }, { DENALI_CTL_01, 0x00000000 },
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