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Searched refs:DDR_TIMING_CFG_4_OFFSET (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/nxp/soc-ls1043a/aarch64/
H A Dls1043a.S34 #define DDR_TIMING_CFG_4_OFFSET 0x160 macro
550 ldr w1, [x6, #DDR_TIMING_CFG_4_OFFSET]
555 str w1, [x6, #DDR_TIMING_CFG_4_OFFSET]
1228 ldr w1, [x6, #DDR_TIMING_CFG_4_OFFSET]
1233 str w1, [x6, #DDR_TIMING_CFG_4_OFFSET]
/rk3399_ARM-atf/plat/nxp/soc-ls1088a/aarch64/
H A Dls1088a.S37 #define DDR_TIMING_CFG_4_OFFSET 0x160 macro