Searched refs:DDR_PHY_BASE (Results 1 – 8 of 8) sorted by relevance
207 fb_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC); in ddr_get_phy_pll_freq()208 fb_div |= (mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGED) & 0x1) << 8; in ddr_get_phy_pll_freq()210 pre_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE) & 0xff; in ddr_get_phy_pll_freq()253 p_ddr_reg->phyaddr = DDR_PHY_BASE; in ddr_reg_save()315 p_ddr_reg->phy.PHY_REG0 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG0); in ddr_reg_save()316 p_ddr_reg->phy.PHY_REG1 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG1); in ddr_reg_save()317 p_ddr_reg->phy.PHY_REGB = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGB); in ddr_reg_save()318 p_ddr_reg->phy.PHY_REGC = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGC); in ddr_reg_save()319 p_ddr_reg->phy.PHY_REG11 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG11); in ddr_reg_save()320 p_ddr_reg->phy.PHY_REG13 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG13); in ddr_reg_save()[all …]
35 return mmio_read_32(DDR_PHY_BASE + offset); in read_phy_reg()40 mmio_write_32(DDR_PHY_BASE + offset, val); in write_phy_reg()
62 #define DDR_PHY_BASE 0xff620000 macro
12 #define DDR_PHY_BASE PLAT_DDR_PHY_BASE macro
67 #define DDR_PHY_BASE 0xff400000 macro
91 #define DDR_PHY_BASE 0xff2a0000 macro
68 MAP_REGION_FLAT(DDR_PHY_BASE, DDR_PHY_SIZE,
47 MAP_REGION_FLAT(DDR_PHY_BASE, DDR_PHY_SIZE,