Searched refs:DDR_GRF_BASE (Results 1 – 6 of 6) sorted by relevance
| /rk3399_ARM-atf/plat/rockchip/rk3576/drivers/dmc/ |
| H A D | suspend.c | 96 mmio_read_32(DDR_GRF_BASE + GRF_CH_CON(ch, 6)) & 0xff7f; in exit_low_power()
97 mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 6), (0x1ul << (15 + 16))); in exit_low_power()
101 mmio_read_32(DDR_GRF_BASE + GRF_CH_CON(ch, 0)) & 0x1f00; in exit_low_power()
102 mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 0), 0x1f000000); in exit_low_power()
110 mmio_read_32(DDR_GRF_BASE + GRF_CH_CON(ch, 1)) & 0x90e6; in exit_low_power()
111 mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 1), 0x90e60000); in exit_low_power()
120 mmio_read_32(DDR_GRF_BASE + GRF_DDRPHY_CON0(ch)) & BIT(14); in exit_low_power()
121 mmio_write_32(DDR_GRF_BASE + GRF_DDRPHY_CON0(ch), BIT(14 + 16)); in exit_low_power()
142 mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 6), in resume_low_power()
149 mmio_write_32(DDR_GRF_BASE + GRF_CH_CON(ch, 0), in resume_low_power()
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| /rk3399_ARM-atf/plat/rockchip/rk3328/drivers/pmu/ |
| H A D | pmu.c | 498 sram_data.ddr_grf_con0 = mmio_read_32(DDR_GRF_BASE + in ddr_suspend()
500 mmio_write_32(DDR_GRF_BASE, BIT_WITH_WMSK(14) | WMSK_BIT(15)); in ddr_suspend()
510 while ((mmio_read_32(DDR_GRF_BASE + DDRGRF_SOC_STATUS(1)) & in ddr_suspend()
547 while ((mmio_read_32(DDR_GRF_BASE + DDRGRF_SOC_STATUS(1)) & in dmc_restore()
551 mmio_write_32(DDR_GRF_BASE, sram_data.ddr_grf_con0 | 0xc0000000); in dmc_restore()
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| /rk3399_ARM-atf/plat/rockchip/rk3328/ |
| H A D | rk3328_def.h | 88 #define DDR_GRF_BASE 0xff798000 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/ |
| H A D | pmu.c | 583 mmio_read_32(DDR_GRF_BASE + DDRGRF_CHA_CON(2)); in ddr_sleep_config()
585 mmio_read_32(DDR_GRF_BASE + DDRGRF_CHB_CON(2)); in ddr_sleep_config()
587 mmio_write_32(DDR_GRF_BASE + DDRGRF_CHA_CON(2), 0x0a000a00); in ddr_sleep_config()
588 mmio_write_32(DDR_GRF_BASE + DDRGRF_CHB_CON(2), 0x0a000a00); in ddr_sleep_config()
593 mmio_write_32(DDR_GRF_BASE + DDRGRF_CHA_CON(2), in ddr_sleep_config_restore()
595 mmio_write_32(DDR_GRF_BASE + DDRGRF_CHB_CON(2), in ddr_sleep_config_restore()
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| /rk3399_ARM-atf/plat/rockchip/rk3576/ |
| H A D | rk3576_def.h | 38 #define DDR_GRF_BASE 0x26012000 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/ |
| H A D | soc.c | 56 MAP_REGION_FLAT(DDR_GRF_BASE, DDR_GRF_SIZE,
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