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Searched refs:DDRPHY_R18 (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/drivers/renesas/rza/ddr/
H A Dddr.c491 write_phy_reg(DDRPHY_R18, 0x50200000); in exec_trainingWRLVL()
494 while ((read_phy_reg(DDRPHY_R18) & 0x10000000) != 0x00000000) in exec_trainingWRLVL()
562 write_phy_reg(DDRPHY_R18, 0x30800000); in exec_trainingVREF()
563 while ((read_phy_reg(DDRPHY_R18) & 0x10000000) != 0x00000000) in exec_trainingVREF()
619 write_phy_reg(DDRPHY_R18, 0x30800000); in exec_trainingVREF()
620 while ((read_phy_reg(DDRPHY_R18) & 0x10000000) != 0x00000000) in exec_trainingVREF()
674 write_phy_reg(DDRPHY_R18, 0x30500000); in exec_trainingVREF()
675 while ((read_phy_reg(DDRPHY_R18) & 0x10000000) != 0x00000000) in exec_trainingVREF()
809 write_phy_reg(DDRPHY_R18, 0x30A00000); in exec_trainingBITLVL()
812 while ((read_phy_reg(DDRPHY_R18) & 0x10000000) != 0x00000000) in exec_trainingBITLVL()
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/rk3399_ARM-atf/plat/renesas/rza/soc/rza3m/include/
H A Dddr_phy_regs.h32 #define DDRPHY_R18 0x100 macro