Searched refs:D2 (Results 1 – 3 of 3) sorted by relevance
7 * DHCM-STM32MP157C-C065-R102-F0819-SPI-E2-CAN2-SDR104-RTC-WBT-T-DSI-I-01D2
95 address 0x1000, CPU 2's cache holds data values D1, D2, D3, and D4
6780 #define D2 0x200U macro