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Searched refs:CSR_SEQ0BDLY2_ADDR (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/src/
H A Dddrphy_phyinit_i_loadpieimage.c94 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY2_ADDR))), in seq0bdly_program()
/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/include/
H A Dddrphy_csr_all_cdefines.h122 #define CSR_SEQ0BDLY2_ADDR 0xDU macro