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Searched refs:CRF_APB_CLK_BASE (Results 1 – 1 of 1) sorted by relevance

/rk3399_ARM-atf/plat/xilinx/zynqmp/include/
H A Dzynqmp_def.h53 #define CRF_APB_CLK_BASE U(0xFD1A0020) macro
273 #define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00)
274 #define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c)
275 #define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18)
276 #define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24)
277 #define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28)
278 #define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c)
279 #define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30)
281 #define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40)
282 #define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44)
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