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Searched refs:CLK_SET_RATE_PARENT (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dpm_api_clock.c153 CLK_SET_RATE_PARENT | \
180 .clkflags = (uint16_t)(CLK_SET_RATE_PARENT | \
193 .clkflags = (uint16_t)(CLK_SET_RATE_PARENT | \
293 .clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT),
306 CLK_SET_RATE_PARENT |
332 CLK_SET_RATE_PARENT |
391 CLK_SET_RATE_PARENT | CLK_IS_BASIC),
400 .clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
411 .clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
422 .clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
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H A Dpm_api_clock.h35 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ macro
/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32-core.h119 #define CLK_SET_RATE_PARENT BIT(2) macro
299 .flags = (CLK_SET_RATE_PARENT | (_flags)),\
/rk3399_ARM-atf/docs/
H A Dchange-log.md10751 function, support to query max divisor, CLK_SET_RATE_PARENT in gem clock