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Searched refs:CLK_SET_RATE_GATE (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dpm_api_clock.h33 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ macro
H A Dpm_api_clock.c181 CLK_SET_RATE_GATE | \
423 CLK_SET_RATE_GATE |
440 CLK_SET_RATE_GATE),