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Searched refs:CLK_DIVIDER_MAX_AT_ZERO (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dpm_api_clock.h54 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) macro
/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32-core.h127 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) macro
H A Dclk-stm32-core.c264 if ((flags & CLK_DIVIDER_MAX_AT_ZERO) != 0UL) { in _get_div()