Searched refs:C0 (Results 1 – 5 of 5) sorted by relevance
36 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | C0 | in dfiwrrddatacsconfig_program()88 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY0_ADDR))), in seq0bdly_program()91 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY1_ADDR))), in seq0bdly_program()94 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY2_ADDR))), in seq0bdly_program()97 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY3_ADDR))), in seq0bdly_program()216 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TACSM | CSR_ACSMCTRL13_ADDR))), in traininghwreg_program()224 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TACSM | CSR_ACSMCTRL1_ADDR))), in traininghwreg_program()
491 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (P0 | C0 | TINITENG | R2 |496 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (P0 | C0 | TINITENG | R2 |501 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (P0 | C0 | TINITENG | R2 |784 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TACSM | CSR_ACSMCTRL23_ADDR))),
215 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | C0 | CSR_SEQ0BGPR4_ADDR))), 0U); in procodtctl_program()769 uintptr_t reg = (uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | in dfixlat_program()
6758 #define C0 0x0U macro
5660 …- fix Agilex and N5X clock manager to main PLL C0 ([5f06bff](https://review.trustedfirmware.org/pl…