Searched refs:BUSSCRU_BASE (Results 1 – 3 of 3) sorted by relevance
67 #define BUSSCRU_BASE 0xfd7d8000 macro
1115 if ((mmio_read_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0)) & 0x0800) != 0) { in clk_scmi_sbus_get_rate()1116 div = mmio_read_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0)); in clk_scmi_sbus_get_rate()1129 mmio_write_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0), in clk_scmi_sbus_set_rate()1135 mmio_write_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0), in clk_scmi_sbus_set_rate()1137 mmio_write_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0), in clk_scmi_sbus_set_rate()1151 div = mmio_read_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0)); in clk_scmi_pclk_sbus_get_rate()1162 mmio_write_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0), in clk_scmi_pclk_sbus_set_rate()1715 src = mmio_read_32(BUSSCRU_BASE + CRU_MODE_CON0) & 0x3; in clk_scmi_spll_get_rate()1737 mmio_write_32(BUSSCRU_BASE + CRU_MODE_CON0, in clk_scmi_spll_set_rate()1739 mmio_write_32(BUSSCRU_BASE + CRU_PLL_CON(137), in clk_scmi_spll_set_rate()[all …]
1265 ddr_data.busscru_mode_con = mmio_read_32(BUSSCRU_BASE + 0x280); in pm_pll_suspend()1281 mmio_write_32(BUSSCRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.busscru_mode_con)); in pm_pll_restore()1337 mmio_write_32(BUSSCRU_BASE + 0x280, 0x0003000); in rockchip_soc_soft_reset()