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Searched refs:BIGCORE1CRU_BASE (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/
H A Dpm_pd_regs.c163 REG_REGION(0x020, 0x034, 4, BIGCORE1CRU_BASE, WMSK_VAL),
164 REG_REGION(0x300, 0x304, 4, BIGCORE1CRU_BASE, WMSK_VAL),
165 REG_REGION(0x800, 0x804, 4, BIGCORE1CRU_BASE, WMSK_VAL),
166 REG_REGION(0xa00, 0xa04, 4, BIGCORE1CRU_BASE, WMSK_VAL),
167 REG_REGION(0xcc0, 0xcc4, 4, BIGCORE1CRU_BASE, 0),
168 REG_REGION(0xd00, 0xd00, 4, BIGCORE1CRU_BASE, 0),
169 REG_REGION(0xd04, 0xd04, 4, BIGCORE1CRU_BASE, WMSK_VAL),
476 b1_cru_mode = mmio_read_32(BIGCORE1CRU_BASE + 0x280); in pd_dsu_core_save()
479 bcore1_cru_sel_con2 = mmio_read_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2)); in pd_dsu_core_save()
489 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2), in pd_dsu_core_restore()
[all …]
H A Dpmu.c780 mmio_write_32(BIGCORE1CRU_BASE + 0xa00, BITS_WITH_WMASK(0, bcore1_rst_msk, 0)); in nonboot_cpus_off()
1330 mmio_write_32(BIGCORE1CRU_BASE + 0x280, 0x00030000); in rockchip_soc_soft_reset()
1331 mmio_write_32(BIGCORE1CRU_BASE + 0x300, 0x60000000); in rockchip_soc_soft_reset()
1332 mmio_write_32(BIGCORE1CRU_BASE + 0x304, 0x00600000); in rockchip_soc_soft_reset()
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/
H A Drk3588_clk.c630 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), in clk_scmi_b1pll_disable()
633 mmio_write_32(BIGCORE1CRU_BASE + CRU_MODE_CON0, CPU_PLL_PATH_SLOWMODE); in clk_scmi_b1pll_disable()
635 mmio_write_32(BIGCORE1CRU_BASE + CRU_PLL_CON(9), CRU_PLL_POWER_DOWN); in clk_scmi_b1pll_disable()
674 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2), in clk_cpub23_set_rate()
676 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), in clk_cpub23_set_rate()
678 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(1), in clk_cpub23_set_rate()
685 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), in clk_cpub23_set_rate()
687 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(1), in clk_cpub23_set_rate()
690 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), in clk_cpub23_set_rate()
692 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), in clk_cpub23_set_rate()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3588/
H A Drk3588_def.h77 #define BIGCORE1CRU_BASE 0xfd812000 macro