Searched refs:BIGCORE0GRF_BASE (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/ |
| H A D | pm_pd_regs.c | 182 REG_REGION(0x20, 0x20, 4, BIGCORE0GRF_BASE, WMSK_VAL),
183 REG_REGION(0x28, 0x30, 4, BIGCORE0GRF_BASE, WMSK_VAL),
502 mmio_write_32(BIGCORE0GRF_BASE + 0x30, BITS_WITH_WMASK(1, 0x1, 5)); in pd_dsu_core_restore()
507 mmio_write_32(BIGCORE0GRF_BASE + 0x30, BITS_WITH_WMASK(0, 0x1, 5)); in pd_dsu_core_restore()
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| /rk3399_ARM-atf/plat/rockchip/rk3588/ |
| H A D | rk3588_def.h | 34 #define BIGCORE0GRF_BASE 0xfd590000 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/ |
| H A D | rk3588_clk.c | 487 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON2, in clk_cpub01_set_rate()
490 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L, in clk_cpub01_set_rate()
493 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON0_H, in clk_cpub01_set_rate()
496 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON1, in clk_cpub01_set_rate()
499 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L, in clk_cpub01_set_rate()
502 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L, in clk_cpub01_set_rate()
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