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Searched refs:BIGCORE0CRU_BASE (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/
H A Dpm_pd_regs.c154 REG_REGION(0x000, 0x014, 4, BIGCORE0CRU_BASE, WMSK_VAL),
155 REG_REGION(0x300, 0x304, 4, BIGCORE0CRU_BASE, WMSK_VAL),
156 REG_REGION(0x800, 0x804, 4, BIGCORE0CRU_BASE, WMSK_VAL),
157 REG_REGION(0xa00, 0xa04, 4, BIGCORE0CRU_BASE, WMSK_VAL),
158 REG_REGION(0xcc0, 0xcc4, 4, BIGCORE0CRU_BASE, 0),
159 REG_REGION(0xd00, 0xd00, 4, BIGCORE0CRU_BASE, 0),
160 REG_REGION(0xd04, 0xd04, 4, BIGCORE0CRU_BASE, WMSK_VAL),
475 b0_cru_mode = mmio_read_32(BIGCORE0CRU_BASE + 0x280); in pd_dsu_core_save()
478 bcore0_cru_sel_con2 = mmio_read_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2)); in pd_dsu_core_save()
487 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2), in pd_dsu_core_restore()
[all …]
H A Dpmu.c779 mmio_write_32(BIGCORE0CRU_BASE + 0xa00, BITS_WITH_WMASK(0, bcore0_rst_msk, 0)); in nonboot_cpus_off()
1327 mmio_write_32(BIGCORE0CRU_BASE + 0x280, 0x00030000); in rockchip_soc_soft_reset()
1328 mmio_write_32(BIGCORE0CRU_BASE + 0x300, 0x60000000); in rockchip_soc_soft_reset()
1329 mmio_write_32(BIGCORE0CRU_BASE + 0x304, 0x00600000); in rockchip_soc_soft_reset()
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/
H A Drk3588_clk.c461 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), in clk_scmi_b0pll_disable()
464 mmio_write_32(BIGCORE0CRU_BASE + CRU_MODE_CON0, CPU_PLL_PATH_SLOWMODE); in clk_scmi_b0pll_disable()
466 mmio_write_32(BIGCORE0CRU_BASE + CRU_PLL_CON(1), CRU_PLL_POWER_DOWN); in clk_scmi_b0pll_disable()
505 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2), in clk_cpub01_set_rate()
507 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), in clk_cpub01_set_rate()
509 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(1), in clk_cpub01_set_rate()
516 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), in clk_cpub01_set_rate()
518 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(1), in clk_cpub01_set_rate()
521 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), in clk_cpub01_set_rate()
523 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), in clk_cpub01_set_rate()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3588/
H A Drk3588_def.h76 #define BIGCORE0CRU_BASE 0xfd810000 macro