Searched refs:reg_name (Results 1 – 2 of 2) sorted by relevance
| /optee_os/scripts/ |
| H A D | arm32_sysreg.py | 22 def gen_read64_macro(reg_name, opc1, crm, descr): argument
26 print('\t.macro read_' + reg_name.lower() + ' reg0, reg1')
31 def gen_write64_macro(reg_name, opc1, crm, descr): argument
35 print('\t.macro write_' + reg_name.lower() + ' reg0, reg1')
40 def gen_read32_macro(reg_name, crn, opc1, crm, opc2, descr): argument
44 print('\t.macro read_' + reg_name.lower() + ' reg')
49 def gen_write32_macro(reg_name, crn, opc1, crm, opc2, descr): argument
53 print('\t.macro write_' + reg_name.lower() + ' reg')
58 def gen_write32_dummy_macro(reg_name, crn, opc1, crm, opc2, descr): argument
62 print('\t.macro write_' + reg_name.lower())
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| /optee_os/core/drivers/crypto/hisilicon/ |
| H A D | hisi_qm.c | 117 const char *reg_name; member
122 { .reg_name = "QM_ECC_1BIT_CNT ", .reg_offset = 0x104000 },
123 { .reg_name = "QM_ECC_MBIT_CNT ", .reg_offset = 0x104008 },
124 { .reg_name = "QM_DFX_MB_CNT ", .reg_offset = 0x104018 },
125 { .reg_name = "QM_DFX_DB_CNT ", .reg_offset = 0x104028 },
126 { .reg_name = "QM_DFX_SQE_CNT ", .reg_offset = 0x104038 },
127 { .reg_name = "QM_DFX_CQE_CNT ", .reg_offset = 0x104048 },
128 { .reg_name = "QM_DFX_SEND_SQE_TO_ACC_CNT", .reg_offset = 0x104050 },
129 { .reg_name = "QM_DFX_WB_SQE_FROM_ACC_CNT", .reg_offset = 0x104058 },
130 { .reg_name = "QM_DFX_ACC_FINISH_CNT ", .reg_offset = 0x104060 },
[all …]
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