Home
last modified time | relevance | path

Searched refs:io_base (Results 1 – 4 of 4) sorted by relevance

/optee_os/core/drivers/crypto/hisilicon/
H A Dhpre_main.c140 io_write32(qm->io_base + HPRE_CORE_ENB, HPRE_CLUSTER_CORE_MASK); in hpre_set_cluster()
141 io_write32(qm->io_base + HPRE_CORE_INI_CFG, 0x1); in hpre_set_cluster()
143 if (IO_READ32_POLL_TIMEOUT(qm->io_base + HPRE_CORE_INI_STATUS, val, in hpre_set_cluster()
153 io_write32(qm->io_base + HPRE_CLKGATE_CTL, 0x0); in hpre_disable_clock_gate()
154 io_write32(qm->io_base + HPRE_PEH_CFG_AUTO_GATE, 0x0); in hpre_disable_clock_gate()
155 io_write32(qm->io_base + HPRE_CLUSTER_DYN_CTL, 0x0); in hpre_disable_clock_gate()
156 io_clrbits32(qm->io_base + HPRE_CORE_SHB_CFG, HPRE_CORE_GATE_ENABLE); in hpre_disable_clock_gate()
161 io_write32(qm->io_base + HPRE_CLKGATE_CTL, 0x1); in hpre_enable_clock_gate()
162 io_write32(qm->io_base + HPRE_PEH_CFG_AUTO_GATE, 0x1); in hpre_enable_clock_gate()
163 io_write32(qm->io_base + HPRE_CLUSTER_DYN_CTL, 0x1); in hpre_enable_clock_gate()
[all …]
H A Dsec_main.c93 io_setbits32(qm->io_base + SEC_CONTROL_REG, SEC_CLK_GATE_ENABLE); in sec_enable_clock_gate()
94 io_write32(qm->io_base + SEC_DYNAMIC_GATE_V3, SEC_DYNAMIC_GATE_EN); in sec_enable_clock_gate()
95 io_write32(qm->io_base + SEC_CORE_AUTO_GATE_V3, SEC_CORE_AUTO_GATE_EN); in sec_enable_clock_gate()
107 io_clrbits32(qm->io_base + SEC_CONTROL_REG, SEC_CLK_GATE_ENABLE); in sec_engine_init()
111 io_write32(qm->io_base + SEC_MEM_START_INIT, 0x1); in sec_engine_init()
112 if (IO_READ32_POLL_TIMEOUT(qm->io_base + SEC_MEM_INIT_DONE, val, in sec_engine_init()
118 io_setbits32(qm->io_base + SEC_CONTROL_REG, sec_dev->endian); in sec_engine_init()
122 io_write32(qm->io_base + SEC_INTERFACE_USER_CTRL0, in sec_engine_init()
124 io_write32(qm->io_base + SEC_INTERFACE_USER_CTRL1, in sec_engine_init()
126 io_write32(qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS, in sec_engine_init()
[all …]
H A Dhisi_qm.c137 qm->version = io_read32(qm->io_base + HISI_QM_REVISON_ID_BASE) & in hisi_qm_get_version()
151 io_write64(qm->io_base + QM_DOORBELL_SQ_CQ_BASE, doorbell); in qm_db()
156 vaddr_t dst = qm->io_base + QM_MAILBOX_BASE; in qm_mb_write()
164 vaddr_t mb_base = qm->io_base + QM_MAILBOX_BASE; in qm_mb_read()
282 io_write32(qm->io_base + QM_VFT_CFG_DATA_L, data_l); in qm_cfg_vft_data()
283 io_write32(qm->io_base + QM_VFT_CFG_DATA_H, data_h); in qm_cfg_vft_data()
294 if (IO_READ32_POLL_TIMEOUT(qm->io_base + QM_VFT_CFG_RDY, val, in qm_set_vft_common()
301 io_write32(qm->io_base + QM_VFT_CFG_OP_WR, QM_VFT_WRITE); in qm_set_vft_common()
302 io_write32(qm->io_base + QM_VFT_CFG_TYPE, vft_type); in qm_set_vft_common()
303 io_write32(qm->io_base + QM_VFT_CFG_ADDRESS, function); in qm_set_vft_common()
[all …]
H A Dhisi_qm.h159 vaddr_t io_base; member
199 vaddr_t io_base; member