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Searched refs:a1 (Results 1 – 25 of 65) sorted by relevance

123

/optee_os/lib/libutils/isoc/arch/arm/
H A Dsetjmp_a32.S207 stmea a1!, { v1-v7, fp, ip, lr }
209 stmea a1!, { v1-v7, fp, ip}
210 str sp, [a1], #4
211 str lr, [a1], #4
217 sfmea f4, 4, [a1]
227 add a1, a1, #48
233 mov a1, #0
246 stmdb sp!, { a1, a2, lr }
251 add a1, a1, #92
253 ldmia sp!, { a1, a2, lr }
[all …]
/optee_os/core/arch/arm/tee/
H A Dentry_fast.c22 args->a1 = default_nsec_shm_paddr; in tee_entry_get_shm_config()
34 args->a1 = CFG_TEE_SDP_MEM_BASE; in tee_entry_get_protmem_config()
38 args->a1 = TEE_SDP_TEST_MEM_BASE; in tee_entry_get_protmem_config()
42 args->a1 = 0; in tee_entry_get_protmem_config()
55 switch (args->a1) { in tee_entry_fastcall_l2cc_mutex()
104 if (args->a1 & ~OPTEE_SMC_NSEC_CAP_UNIPROCESSOR) { in tee_entry_exchange_capabilities()
111 args->a1 = 0; in tee_entry_exchange_capabilities()
114 args->a1 |= OPTEE_SMC_SEC_CAP_HAVE_RESERVED_SHM; in tee_entry_exchange_capabilities()
120 args->a1 |= OPTEE_SMC_SEC_CAP_DYNAMIC_SHM; in tee_entry_exchange_capabilities()
125 args->a1 |= OPTEE_SMC_SEC_CAP_VIRTUALIZATION; in tee_entry_exchange_capabilities()
[all …]
/optee_os/core/lib/libtomcrypt/src/pk/asn1/der/sequence/
H A Dder_decode_sequence_multi.c23 static int s_der_decode_sequence_va(const unsigned char *in, unsigned long inlen, va_list a1, va_li… in s_der_decode_sequence_va() argument
36 type = (ltc_asn1_type)va_arg(a1, int); in s_der_decode_sequence_va()
42 size = va_arg(a1, unsigned long); in s_der_decode_sequence_va()
43 data = va_arg(a1, void*); in s_der_decode_sequence_va()
140 va_list a1, a2; in der_decode_sequence_multi() local
145 va_start(a1, inlen); in der_decode_sequence_multi()
148 err = s_der_decode_sequence_va(in, inlen, a1, a2, LTC_DER_SEQ_SEQUENCE | LTC_DER_SEQ_RELAXED); in der_decode_sequence_multi()
151 va_end(a1); in der_decode_sequence_multi()
166 va_list a1, a2; in der_decode_sequence_multi_ex() local
171 va_start(a1, flags); in der_decode_sequence_multi_ex()
[all …]
/optee_os/core/arch/riscv/tee/
H A Dentry_fast.c23 args->a1 = default_nsec_shm_paddr; in tee_entry_get_shm_config()
53 if (args->a1 & ~OPTEE_ABI_NSEC_CAP_UNIPROCESSOR) { in tee_entry_exchange_capabilities()
60 args->a1 = 0; in tee_entry_exchange_capabilities()
63 args->a1 |= OPTEE_ABI_SEC_CAP_HAVE_RESERVED_SHM; in tee_entry_exchange_capabilities()
69 args->a1 |= OPTEE_ABI_SEC_CAP_DYNAMIC_SHM; in tee_entry_exchange_capabilities()
74 args->a1 |= OPTEE_ABI_SEC_CAP_VIRTUALIZATION; in tee_entry_exchange_capabilities()
78 args->a1 |= OPTEE_ABI_SEC_CAP_MEMREF_NULL; in tee_entry_exchange_capabilities()
81 args->a1 |= OPTEE_ABI_SEC_CAP_ASYNC_NOTIF; in tee_entry_exchange_capabilities()
87 args->a1 |= OPTEE_ABI_SEC_CAP_RPC_ARG; in tee_entry_exchange_capabilities()
106 args->a1 = cookie >> 32; in tee_entry_disable_shm_cache()
[all …]
/optee_os/ldelf/
H A Dstart_rv64.S23 lla a1, reloc_end_rel
24 lw a3, 0(a1)
25 lla a1, reloc_begin_rel
26 lw a2, 0(a1)
27 add a2, a2, a1
28 add a3, a3, a1
31 lla a1, _ldelf_start /* Get the load offset */
44 add t1, a1, t1
47 add t4, t4, a1
/optee_os/lib/libutils/ext/arch/riscv/
H A Datomic_rv.S10 li a1, 1
11 amoadd.w.aqrl a2, a1, (a0)
12 add a0, a1, a2
18 li a1, -1
19 amoadd.w.aqrl a2, a1, (a0)
20 add a0, a1, a2
/optee_os/core/arch/arm/sm/
H A Dpsci.c143 uint32_t a1 = args->a1; in tee_psci_handler() local
152 args->a0 = psci_cpu_suspend(a1, a2, a3, nsec); in tee_psci_handler()
158 args->a0 = psci_cpu_on(a1, a2, a3); in tee_psci_handler()
161 args->a0 = psci_affinity_info(a1, a2); in tee_psci_handler()
164 args->a0 = psci_migrate(a1); in tee_psci_handler()
183 args->a0 = psci_features(a1); in tee_psci_handler()
186 args->a0 = psci_system_reset2(a1, a2); in tee_psci_handler()
189 args->a0 = psci_mem_protect(a1); in tee_psci_handler()
192 args->a0 = psci_mem_chk_range(a1, a2); in tee_psci_handler()
195 args->a0 = psci_node_hw_state(a1, a2); in tee_psci_handler()
[all …]
/optee_os/core/arch/riscv/kernel/
H A Dentry.S131 mv s1, a1 /* Save device tree address into s1 */
218 mv a1, sp
219 STR a1, THREAD_CORE_LOCAL_TMP_STACK_VA_END(tp)
231 la a1, __vcore_free_end
234 sub a1, a1, a2
248 la a1, boot_mmu_config
278 LDR a1, THREAD_CORE_LOCAL_TMP_STACK_VA_END(tp)
279 add a1, a1, a0
280 STR a1, THREAD_CORE_LOCAL_TMP_STACK_VA_END(tp)
281 LDR a1, THREAD_CORE_LOCAL_ABT_STACK_VA_END(tp)
[all …]
H A Dthread_arch.c193 static void init_regs(struct thread_ctx *thread, uint32_t a0, uint32_t a1, in init_regs() argument
219 thread->regs.a1 = a1; in init_regs()
228 static void __thread_alloc_and_run(uint32_t a0, uint32_t a1, uint32_t a2, in __thread_alloc_and_run() argument
257 init_regs(threads + n, a0, a1, a2, a3, a4, a5, a6, a7, pc); in __thread_alloc_and_run()
268 void thread_alloc_and_run(uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3, in thread_alloc_and_run() argument
271 __thread_alloc_and_run(a0, a1, a2, a3, a4, a5, 0, 0, in thread_alloc_and_run()
276 uint32_t a1, uint32_t a2, uint32_t a3) in copy_a0_to_a3() argument
279 regs->a1 = a1; in copy_a0_to_a3()
336 void thread_resume_from_rpc(uint32_t thread_id, uint32_t a0, uint32_t a1, in thread_resume_from_rpc() argument
380 copy_a0_to_a3(&threads[n].regs, a0, a1, a2, a3); in thread_resume_from_rpc()
[all …]
H A Dthread_optee_abi_rv.S63 mv a1, s0
90 STR a1, REGOFF(1)(sp)
113 LDR a1, REGOFF(1)(sp)
127 mv a1, s2 /* rv[0] */
147 sw a1, 4(a4)
172 mv a1, a0
201 li a1, 0
H A Darch_scall_rv.S26 mv t1, a1
48 li a1, 0 /* panic = false */
58 li a1, 1 /* panic = true */
H A Darch_scall.c62 (uaddr_t)regs->a1, in scall_save_panic_stack()
66 (uaddr_t)regs->a1); in scall_save_panic_stack()
74 save_panic_regs_rv_ta(tsd, (unsigned long *)regs->a1); in scall_save_panic_stack()
/optee_os/lib/libutils/isoc/newlib/
H A Dstrcmp.c107 unsigned long *a1;
115 a1 = (unsigned long *)s1;
117 while (*a1 == *a2) {
122 if (DETECTNULL(*a1))
125 a1++;
133 s1 = (char *)a1;
H A Dstrncmp.c115 unsigned long *a1;
125 a1 = (unsigned long*)s1;
127 while (n >= sizeof (long) && *a1 == *a2)
133 if (n == 0 || DETECTNULL (*a1))
136 a1++;
141 s1 = (char*)a1;
H A Dmemcmp.c100 unsigned long *a1;
111 a1 = (unsigned long *)s1;
114 if (*a1 != *a2)
116 a1++;
123 s1 = (unsigned char *)a1;
/optee_os/core/arch/arm/plat-ti/
H A Dsm_platform_handler_a9.c38 io_write32(pl310_base() + PL310_DEBUG_CTRL, smc_args->a1); in ti_sip_handler()
42 arm_cl2_cleaninvbypa(pl310_base(), smc_args->a1, in ti_sip_handler()
43 smc_args->a1 + smc_args->a2); in ti_sip_handler()
47 io_write32(pl310_base() + PL310_CTRL, smc_args->a1); in ti_sip_handler()
51 io_write32(pl310_base() + PL310_AUX_CTRL, smc_args->a1); in ti_sip_handler()
55 io_write32(pl310_base() + PL310_TAG_RAM_CTRL, smc_args->a1); in ti_sip_handler()
60 io_write32(pl310_base() + PL310_PREFETCH_CTRL, smc_args->a1); in ti_sip_handler()
H A Dsm_platform_handler_a15.c47 write_actlr(smc_args->a1); in ti_sip_handler()
52 write_cntfrq(smc_args->a1); in ti_sip_handler()
57 write_wugen_mpu_amba_if_mode(smc_args->a1); in ti_sip_handler()
/optee_os/core/arch/riscv/include/
H A Driscv_macros.S58 mv a1, \reg_op1
62 andi a3, a1, 1
66 srli a1, a1, 1
68 bnez a1, 1b
/optee_os/core/arch/riscv/include/kernel/
H A Dthread_private_arch.h89 void thread_std_abi_entry(uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3,
91 uint32_t __thread_std_abi_entry(uint32_t a0, uint32_t a1, uint32_t a2,
103 uint32_t thread_handle_std_abi(uint32_t a0, uint32_t a1, uint32_t a2,
118 void thread_alloc_and_run(uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3,
120 void thread_resume_from_rpc(uint32_t thread_id, uint32_t a0, uint32_t a1,
/optee_os/core/arch/arm/include/kernel/
H A Dthread_arch.h102 uint32_t a1; /* Parameter */ member
115 uint32_t a1; member
131 uint64_t a1; /* Parameter */ member
144 uint64_t a1; member
339 unsigned long thread_cpu_off_handler(unsigned long a0, unsigned long a1);
340 unsigned long thread_cpu_suspend_handler(unsigned long a0, unsigned long a1);
341 unsigned long thread_cpu_resume_handler(unsigned long a0, unsigned long a1);
342 unsigned long thread_system_off_handler(unsigned long a0, unsigned long a1);
343 unsigned long thread_system_reset_handler(unsigned long a0, unsigned long a1);
506 unsigned long thread_hvc(unsigned long func_id, unsigned long a1,
[all …]
H A Dthread_private_arch.h128 void thread_std_smc_entry(uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3,
130 uint32_t __thread_std_smc_entry(uint32_t a0, uint32_t a1, uint32_t a2,
190 void thread_alloc_and_run(uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3,
192 void thread_resume_from_rpc(uint32_t thread_id, uint32_t a0, uint32_t a1,
251 uint32_t thread_handle_std_smc(uint32_t a0, uint32_t a1, uint32_t a2,
/optee_os/core/arch/arm/tests/
H A Dffa_lsp.c13 uint16_t src = args->a1 >> 16; in test_direct_req()
14 uint16_t dst = args->a1; in test_direct_req()
20 args->a1 = SHIFT_U32(dst, 16) | src; in test_direct_req()
/optee_os/core/arch/arm/plat-stm32mp2/
H A Dstm32mp_pm.c21 unsigned long a1 __unused) in thread_system_off_handler()
59 unsigned long a1 __unused) in thread_cpu_resume_handler()
84 unsigned long a1 __unused) in thread_cpu_suspend_handler()
/optee_os/core/arch/arm/kernel/
H A Dthread.c151 static void init_regs(struct thread_ctx *thread, uint32_t a0, uint32_t a1, in init_regs() argument
175 thread->regs.r1 = a1; in init_regs()
186 static void init_regs(struct thread_ctx *thread, uint32_t a0, uint32_t a1, in init_regs() argument
206 thread->regs.x[1] = a1; in init_regs()
219 static void __thread_alloc_and_run(uint32_t a0, uint32_t a1, uint32_t a2, in __thread_alloc_and_run() argument
248 init_regs(threads + n, a0, a1, a2, a3, a4, a5, a6, a7, pc); in __thread_alloc_and_run()
266 void thread_alloc_and_run(uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3, in thread_alloc_and_run() argument
269 __thread_alloc_and_run(a0, a1, a2, a3, a4, a5, 0, 0, in thread_alloc_and_run()
276 __thread_alloc_and_run(args->a0, args->a1, args->a2, args->a3, args->a4, in thread_sp_alloc_and_run()
284 uint32_t a1, uint32_t a2, uint32_t a3) in copy_a0_to_a3() argument
[all …]
/optee_os/core/drivers/
H A Dsmccc_trng.c81 args.a1 = ARM_SMCCC_TRNG_RND_64; in smccc_trng_is_supported()
90 args.a1 = ARM_SMCCC_TRNG_RND_32; in smccc_trng_is_supported()
126 read_bytes(args->a1, byte_count, &ptr, &rem); in read_samples()
148 args.a1 = burst * 8; in smccc_trng_read()
188 major, minor, (unsigned long)args.a0, (unsigned long)args.a1 >> 16, in smccc_trng_print_info()
189 (unsigned long)args.a1 & GENMASK_32(16, 0), in smccc_trng_print_info()

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