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Searched refs:SEC_RAS_CE_ENABLE (Results 1 – 1 of 1) sorted by relevance

/optee_os/core/drivers/crypto/hisilicon/
H A Dsec_main.c19 #define SEC_RAS_CE_ENABLE 0x301050 macro
147 io_write32(qm->io_base + SEC_RAS_CE_ENABLE, SEC_RAS_CE_ENB_MASK); in sec_engine_init()